379 lines
13 KiB
Text
379 lines
13 KiB
Text
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64-- -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
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# RUN: llc -debugify-and-strip-all-safe -mtriple=aarch64-- -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
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---
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name: test_memcpy
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $w2, $x0, $x1
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; CHECK-LABEL: name: test_memcpy
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; CHECK: liveins: $w2, $x0, $x1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
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; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY2]](s32)
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; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
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; CHECK-NEXT: $x0 = COPY [[COPY]](p0)
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; CHECK-NEXT: $x1 = COPY [[COPY1]](p0)
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; CHECK-NEXT: $x2 = COPY [[ZEXT]](s64)
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; CHECK-NEXT: BL &memcpy, csr_aarch64_aapcs_thisreturn, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2
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; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
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; CHECK-NEXT: RET_ReallyLR
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%0:_(p0) = COPY $x0
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%1:_(p0) = COPY $x1
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%2:_(s32) = COPY $w2
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%3:_(s64) = G_ZEXT %2(s32)
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G_MEMCPY %0(p0), %1(p0), %3(s64), 0 :: (store unknown-size), (load unknown-size)
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RET_ReallyLR
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...
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---
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name: test_memcpy_tail
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $w2, $x0, $x1
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; CHECK-LABEL: name: test_memcpy_tail
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; CHECK: liveins: $w2, $x0, $x1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
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; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY2]](s32)
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; CHECK-NEXT: $x0 = COPY [[COPY]](p0)
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; CHECK-NEXT: $x1 = COPY [[COPY1]](p0)
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; CHECK-NEXT: $x2 = COPY [[ZEXT]](s64)
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; CHECK-NEXT: TCRETURNdi &memcpy, 0, csr_aarch64_aapcs, implicit $sp, implicit $x0, implicit $x1, implicit $x2
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%0:_(p0) = COPY $x0
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%1:_(p0) = COPY $x1
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%2:_(s32) = COPY $w2
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%3:_(s64) = G_ZEXT %2(s32)
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G_MEMCPY %0(p0), %1(p0), %3(s64), 1 :: (store unknown-size), (load unknown-size)
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RET_ReallyLR
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...
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---
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name: test_memmove
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $w2, $x0, $x1
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; CHECK-LABEL: name: test_memmove
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; CHECK: liveins: $w2, $x0, $x1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
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; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY2]](s32)
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; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
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; CHECK-NEXT: $x0 = COPY [[COPY]](p0)
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; CHECK-NEXT: $x1 = COPY [[COPY1]](p0)
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; CHECK-NEXT: $x2 = COPY [[ZEXT]](s64)
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; CHECK-NEXT: BL &memmove, csr_aarch64_aapcs_thisreturn, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2
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; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
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; CHECK-NEXT: RET_ReallyLR
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%0:_(p0) = COPY $x0
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%1:_(p0) = COPY $x1
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%2:_(s32) = COPY $w2
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%3:_(s64) = G_ZEXT %2(s32)
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G_MEMMOVE %0(p0), %1(p0), %3(s64), 0 :: (store unknown-size), (load unknown-size)
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RET_ReallyLR
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...
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---
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name: test_memset
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $w1, $w2, $x0
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; CHECK-LABEL: name: test_memset
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; CHECK: liveins: $w1, $w2, $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
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; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY2]](s32)
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; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
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; CHECK-NEXT: $x0 = COPY [[COPY]](p0)
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; CHECK-NEXT: $w1 = COPY [[COPY1]](s32)
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; CHECK-NEXT: $x2 = COPY [[ZEXT]](s64)
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; CHECK-NEXT: BL &memset, csr_aarch64_aapcs_thisreturn, implicit-def $lr, implicit $sp, implicit $x0, implicit $w1, implicit $x2
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; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
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; CHECK-NEXT: RET_ReallyLR
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%0:_(p0) = COPY $x0
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%1:_(s32) = COPY $w1
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%2:_(s32) = COPY $w2
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%3:_(s8) = G_TRUNC %1(s32)
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%4:_(s64) = G_ZEXT %2(s32)
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G_MEMSET %0(p0), %3(s8), %4(s64), 0 :: (store unknown-size)
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RET_ReallyLR
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...
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---
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name: no_tail_call
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $w2, $x0, $x1
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; CHECK-LABEL: name: no_tail_call
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; CHECK: liveins: $w2, $x0, $x1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x1
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
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; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY2]](s32)
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; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
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; CHECK-NEXT: $x0 = COPY [[COPY]](p0)
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; CHECK-NEXT: $x1 = COPY [[COPY1]](p0)
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; CHECK-NEXT: $x2 = COPY [[ZEXT]](s64)
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; CHECK-NEXT: BL &memcpy, csr_aarch64_aapcs_thisreturn, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2
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; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
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; CHECK-NEXT: $x0 = COPY [[ZEXT]](s64)
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; CHECK-NEXT: RET_ReallyLR implicit $x0
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%0:_(p0) = COPY $x1
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%1:_(p0) = COPY $x0
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%2:_(s32) = COPY $w2
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%3:_(s64) = G_ZEXT %2(s32)
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G_MEMCPY %0(p0), %1(p0), %3(s64), 1 :: (store unknown-size), (load unknown-size)
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$x0 = COPY %3
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RET_ReallyLR implicit $x0
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...
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---
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name: dont_tc_twice
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $w2, $x0, $x1
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; CHECK-LABEL: name: dont_tc_twice
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; CHECK: liveins: $w2, $x0, $x1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
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; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY2]](s32)
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; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
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; CHECK-NEXT: $x0 = COPY [[COPY]](p0)
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; CHECK-NEXT: $x1 = COPY [[COPY1]](p0)
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; CHECK-NEXT: $x2 = COPY [[ZEXT]](s64)
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; CHECK-NEXT: BL &memcpy, csr_aarch64_aapcs_thisreturn, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2
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; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
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; CHECK-NEXT: TCRETURNdi &memset, 0, csr_aarch64_aapcs, implicit $sp
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%0:_(p0) = COPY $x0
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%1:_(p0) = COPY $x1
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%2:_(s32) = COPY $w2
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%4:_(s1) = G_CONSTANT i1 false
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%3:_(s64) = G_ZEXT %2(s32)
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G_MEMCPY %0(p0), %1(p0), %3(s64), 1 :: (store unknown-size), (load unknown-size)
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TCRETURNdi &memset, 0, csr_aarch64_aapcs, implicit $sp
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...
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---
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name: tail_with_copy_ret
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alignment: 4
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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liveins:
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- { reg: '$x0' }
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- { reg: '$x1' }
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- { reg: '$x2' }
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo: {}
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body: |
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bb.1.entry:
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liveins: $x0, $x1, $x2
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; CHECK-LABEL: name: tail_with_copy_ret
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; CHECK: liveins: $x0, $x1, $x2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
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; CHECK-NEXT: $x0 = COPY [[COPY]](p0)
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; CHECK-NEXT: $x1 = COPY [[COPY1]](p0)
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; CHECK-NEXT: $x2 = COPY [[COPY2]](s64)
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; CHECK-NEXT: TCRETURNdi &memcpy, 0, csr_aarch64_aapcs, implicit $sp, implicit $x0, implicit $x1, implicit $x2
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%0:_(p0) = COPY $x0
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%1:_(p0) = COPY $x1
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%2:_(s64) = COPY $x2
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G_MEMCPY %0(p0), %1(p0), %2(s64), 1 :: (store (s8)), (load (s8))
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$x0 = COPY %0(p0)
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RET_ReallyLR implicit $x0
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...
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---
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name: dont_tc_mismatched_copies
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alignment: 4
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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liveins:
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- { reg: '$x0' }
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- { reg: '$x1' }
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- { reg: '$x2' }
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo: {}
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body: |
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bb.1.entry:
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liveins: $x0, $x1, $x2
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; CHECK-LABEL: name: dont_tc_mismatched_copies
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; CHECK: liveins: $x0, $x1, $x2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
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; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
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; CHECK-NEXT: $x0 = COPY [[COPY]](p0)
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; CHECK-NEXT: $x1 = COPY [[COPY1]](p0)
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; CHECK-NEXT: $x2 = COPY [[COPY2]](s64)
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; CHECK-NEXT: BL &memcpy, csr_aarch64_aapcs_thisreturn, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2
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; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
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; CHECK-NEXT: $x1 = COPY [[COPY]](p0)
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; CHECK-NEXT: RET_ReallyLR implicit $x0
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%0:_(p0) = COPY $x0
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%1:_(p0) = COPY $x1
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%2:_(s64) = COPY $x2
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G_MEMCPY %0(p0), %1(p0), %2(s64), 1 :: (store (s8)), (load (s8))
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$x1 = COPY %0(p0)
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RET_ReallyLR implicit $x0
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...
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---
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name: dont_tc_extra_copy
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alignment: 4
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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liveins:
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- { reg: '$x0' }
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- { reg: '$x1' }
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- { reg: '$x2' }
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo: {}
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body: |
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bb.1.entry:
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liveins: $x0, $x1, $x2
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; CHECK-LABEL: name: dont_tc_extra_copy
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; CHECK: liveins: $x0, $x1, $x2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
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; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
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; CHECK-NEXT: $x0 = COPY [[COPY]](p0)
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; CHECK-NEXT: $x1 = COPY [[COPY1]](p0)
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; CHECK-NEXT: $x2 = COPY [[COPY2]](s64)
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; CHECK-NEXT: BL &memcpy, csr_aarch64_aapcs_thisreturn, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2
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; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
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; CHECK-NEXT: $x0 = COPY [[COPY]](p0)
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; CHECK-NEXT: $x0 = COPY [[COPY]](p0)
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|
|
; CHECK-NEXT: RET_ReallyLR implicit $x0
|
||
|
|
%0:_(p0) = COPY $x0
|
||
|
|
%1:_(p0) = COPY $x1
|
||
|
|
%2:_(s64) = COPY $x2
|
||
|
|
G_MEMCPY %0(p0), %1(p0), %2(s64), 1 :: (store (s8)), (load (s8))
|
||
|
|
$x0 = COPY %0(p0)
|
||
|
|
$x0 = COPY %0(p0)
|
||
|
|
RET_ReallyLR implicit $x0
|
||
|
|
|
||
|
|
...
|
||
|
|
---
|
||
|
|
name: dont_tc_mismatched_ret
|
||
|
|
alignment: 4
|
||
|
|
tracksRegLiveness: true
|
||
|
|
registers:
|
||
|
|
- { id: 0, class: _ }
|
||
|
|
- { id: 1, class: _ }
|
||
|
|
- { id: 2, class: _ }
|
||
|
|
liveins:
|
||
|
|
- { reg: '$x0' }
|
||
|
|
- { reg: '$x1' }
|
||
|
|
- { reg: '$x2' }
|
||
|
|
frameInfo:
|
||
|
|
maxAlignment: 1
|
||
|
|
machineFunctionInfo: {}
|
||
|
|
body: |
|
||
|
|
bb.1.entry:
|
||
|
|
liveins: $x0, $x1, $x2
|
||
|
|
|
||
|
|
; CHECK-LABEL: name: dont_tc_mismatched_ret
|
||
|
|
; CHECK: liveins: $x0, $x1, $x2
|
||
|
|
; CHECK-NEXT: {{ $}}
|
||
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x1
|
||
|
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x0
|
||
|
|
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
|
||
|
|
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
|
||
|
|
; CHECK-NEXT: $x0 = COPY [[COPY]](p0)
|
||
|
|
; CHECK-NEXT: $x1 = COPY [[COPY1]](p0)
|
||
|
|
; CHECK-NEXT: $x2 = COPY [[COPY2]](s64)
|
||
|
|
; CHECK-NEXT: BL &memcpy, csr_aarch64_aapcs_thisreturn, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2
|
||
|
|
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
|
||
|
|
; CHECK-NEXT: $x1 = COPY [[COPY]](p0)
|
||
|
|
; CHECK-NEXT: RET_ReallyLR implicit $x0
|
||
|
|
%0:_(p0) = COPY $x1
|
||
|
|
%1:_(p0) = COPY $x0
|
||
|
|
%2:_(s64) = COPY $x2
|
||
|
|
G_MEMCPY %0(p0), %1(p0), %2(s64), 1 :: (store (s8)), (load (s8))
|
||
|
|
$x1 = COPY %0(p0)
|
||
|
|
RET_ReallyLR implicit $x0
|
||
|
|
|
||
|
|
...
|
||
|
|
---
|
||
|
|
name: dont_tc_ret_void_copy
|
||
|
|
alignment: 4
|
||
|
|
tracksRegLiveness: true
|
||
|
|
registers:
|
||
|
|
- { id: 0, class: _ }
|
||
|
|
- { id: 1, class: _ }
|
||
|
|
- { id: 2, class: _ }
|
||
|
|
liveins:
|
||
|
|
- { reg: '$x0' }
|
||
|
|
- { reg: '$x1' }
|
||
|
|
- { reg: '$x2' }
|
||
|
|
frameInfo:
|
||
|
|
maxAlignment: 1
|
||
|
|
machineFunctionInfo: {}
|
||
|
|
body: |
|
||
|
|
bb.1.entry:
|
||
|
|
liveins: $x0, $x1, $x2
|
||
|
|
|
||
|
|
; CHECK-LABEL: name: dont_tc_ret_void_copy
|
||
|
|
; CHECK: liveins: $x0, $x1, $x2
|
||
|
|
; CHECK-NEXT: {{ $}}
|
||
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
|
||
|
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
|
||
|
|
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
|
||
|
|
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
|
||
|
|
; CHECK-NEXT: $x0 = COPY [[COPY]](p0)
|
||
|
|
; CHECK-NEXT: $x1 = COPY [[COPY1]](p0)
|
||
|
|
; CHECK-NEXT: $x2 = COPY [[COPY2]](s64)
|
||
|
|
; CHECK-NEXT: BL &memcpy, csr_aarch64_aapcs_thisreturn, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2
|
||
|
|
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
|
||
|
|
; CHECK-NEXT: $x0 = COPY [[COPY]](p0)
|
||
|
|
; CHECK-NEXT: RET_ReallyLR
|
||
|
|
%0:_(p0) = COPY $x0
|
||
|
|
%1:_(p0) = COPY $x1
|
||
|
|
%2:_(s64) = COPY $x2
|
||
|
|
G_MEMCPY %0(p0), %1(p0), %2(s64), 1 :: (store (s8)), (load (s8))
|
||
|
|
$x0 = COPY %0(p0)
|
||
|
|
RET_ReallyLR
|