61 lines
2.1 KiB
LLVM
61 lines
2.1 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -mtriple=amdgcn-amd-amdhsa -p simplifycfg,amdgpu-unify-divergent-exit-nodes %s -S -o - | FileCheck %s --check-prefix=OPT
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; RUN: llc -mtriple=amdgcn-amd-amdhsa %s -o - | FileCheck %s --check-prefix=ISA
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define void @nested_inf_loop(i1 %0, i1 %1) {
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; OPT-LABEL: @nested_inf_loop(
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; OPT-NEXT: BB:
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; OPT-NEXT: br label [[BB1:%.*]]
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; OPT: BB1:
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; OPT-NEXT: [[BRMERGE:%.*]] = select i1 [[TMP0:%.*]], i1 true, i1 [[TMP1:%.*]]
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; OPT-NEXT: br i1 [[BRMERGE]], label [[BB1]], label [[INFLOOP:%.*]]
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; OPT: infloop:
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; OPT-NEXT: br i1 true, label [[INFLOOP]], label [[DUMMYRETURNBLOCK:%.*]]
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; OPT: DummyReturnBlock:
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; OPT-NEXT: ret void
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;
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; ISA-LABEL: nested_inf_loop:
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; ISA-NEXT: %bb.0: ; %BB
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; ISA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; ISA-NEXT: v_and_b32_e32 v1, 1, v1
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; ISA-NEXT: v_and_b32_e32 v0, 1, v0
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; ISA-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v1
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; ISA-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
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; ISA-NEXT: s_xor_b64 s[6:7], vcc, -1
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; ISA-NEXT: s_mov_b64 s[8:9], 0
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; ISA-NEXT: .LBB0_1: ; %BB1
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; ISA: s_and_b64 s[10:11], exec, s[6:7]
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; ISA-NEXT: s_or_b64 s[8:9], s[10:11], s[8:9]
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; ISA-NEXT: s_andn2_b64 exec, exec, s[8:9]
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; ISA-NEXT: s_cbranch_execnz .LBB0_1
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; ISA-NEXT: %bb.2: ; %BB2
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; ISA: s_or_b64 exec, exec, s[8:9]
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; ISA-NEXT: s_mov_b64 s[8:9], 0
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; ISA-NEXT: .LBB0_3: ; %BB4
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; ISA: s_and_b64 s[10:11], exec, s[4:5]
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; ISA-NEXT: s_or_b64 s[8:9], s[10:11], s[8:9]
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; ISA-NEXT: s_andn2_b64 exec, exec, s[8:9]
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; ISA-NEXT: s_cbranch_execnz .LBB0_3
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; ISA-NEXT: %bb.4: ; %loop.exit.guard
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; ISA: s_or_b64 exec, exec, s[8:9]
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; ISA-NEXT: s_mov_b64 vcc, 0
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; ISA-NEXT: s_mov_b64 s[8:9], 0
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; ISA-NEXT: s_branch .LBB0_1
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; ISA-NEXT: %bb.5: ; %DummyReturnBlock
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; ISA-NEXT: s_setpc_b64 s[30:31]
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BB:
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br label %BB1
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BB1:
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br i1 %0, label %BB3, label %BB2
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BB2:
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br label %BB4
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BB4:
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br i1 %1, label %BB3, label %BB4
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BB3:
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br label %BB1
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}
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