44 lines
1.7 KiB
LLVM
44 lines
1.7 KiB
LLVM
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; RUN: llc -mtriple=riscv64-- -debug-pass=Structure %s -o /dev/null 2>&1 \
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; RUN: -verify-machineinstrs=0 -O0 -global-isel \
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; RUN: | FileCheck %s --check-prefixes=ENABLED,NOFALLBACK,ENABLED-O0
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; RUN: llc -mtriple=riscv64-- -debug-pass=Structure %s -o /dev/null 2>&1 \
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; RUN: -verify-machineinstrs=0 -global-isel \
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; RUN: | FileCheck %s --check-prefixes=ENABLED,NOFALLBACK,ENABLED-O1
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; RUN: llc -mtriple=riscv64-- -debug-pass=Structure %s -o /dev/null 2>&1 \
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; RUN: -verify-machineinstrs=0 -global-isel -global-isel-abort=2 \
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; RUN: | FileCheck %s --check-prefixes=ENABLED,FALLBACK,ENABLED-O1
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; RUN: llc -mtriple=riscv64-- -debug-pass=Structure %s -o /dev/null 2>&1 \
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; RUN: -verify-machineinstrs=0 \
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; RUN: | FileCheck %s --check-prefixes=DISABLED
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; ENABLED: IRTranslator
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; ENABLED-NEXT: Analysis for ComputingKnownBits
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; ENABLED-O0-NEXT: RISCVO0PreLegalizerCombiner
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; ENABLED-O1-NEXT: MachineDominator Tree Construction
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; ENABLED-NEXT: Analysis containing CSE Info
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; ENABLED-O1-NEXT: RISCVPreLegalizerCombiner
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; ENABLED-NEXT: Legalizer
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; ENABLED-O1-NEXT: MachineDominator Tree Construction
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; ENABLED-O1-NEXT: RISCVPostLegalizerCombiner
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; ENABLED-NEXT: RegBankSelect
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; ENABLED-NEXT: Analysis for ComputingKnownBits
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; ENABLED-O1-NEXT: Lazy Branch Probability Analysis
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; ENABLED-O1-NEXT: Lazy Block Frequency Analysis
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; ENABLED-NEXT: InstructionSelect
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; ENABLED-NEXT: ResetMachineFunction
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; FALLBACK: RISC-V DAG->DAG Pattern Instruction Selection
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; NOFALLBACK-NOT: RISC-V DAG->DAG Pattern Instruction Selection
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; DISABLED-NOT: IRTranslator
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; DISABLED: RISC-V DAG->DAG Pattern Instruction Selection
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; DISABLED: Finalize ISel and expand pseudo-instructions
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define void @empty() {
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ret void
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}
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