67 lines
2.3 KiB
C++
67 lines
2.3 KiB
C++
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//===- TestLoopMapping.cpp --- Parametric loop mapping pass ---------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements a pass to parametrically map scf.for loops to virtual
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// processing element dimensions.
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//
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//===----------------------------------------------------------------------===//
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#include "mlir/Dialect/Affine/IR/AffineOps.h"
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#include "mlir/Dialect/Affine/LoopUtils.h"
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#include "mlir/Dialect/SCF/IR/SCF.h"
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#include "mlir/IR/Builders.h"
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#include "mlir/Pass/Pass.h"
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using namespace mlir;
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using namespace mlir::affine;
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namespace {
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struct TestLoopMappingPass
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: public PassWrapper<TestLoopMappingPass, OperationPass<>> {
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MLIR_DEFINE_EXPLICIT_INTERNAL_INLINE_TYPE_ID(TestLoopMappingPass)
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StringRef getArgument() const final {
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return "test-mapping-to-processing-elements";
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}
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StringRef getDescription() const final {
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return "test mapping a single loop on a virtual processor grid";
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}
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explicit TestLoopMappingPass() = default;
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void getDependentDialects(DialectRegistry ®istry) const override {
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registry.insert<affine::AffineDialect, scf::SCFDialect>();
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}
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void runOnOperation() override {
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// SSA values for the transformation are created out of thin air by
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// unregistered "new_processor_id_and_range" operations. This is enough to
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// emulate mapping conditions.
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SmallVector<Value, 8> processorIds, numProcessors;
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getOperation()->walk([&processorIds, &numProcessors](Operation *op) {
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if (op->getName().getStringRef() != "new_processor_id_and_range")
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return;
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processorIds.push_back(op->getResult(0));
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numProcessors.push_back(op->getResult(1));
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});
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getOperation()->walk([&processorIds, &numProcessors](scf::ForOp op) {
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// Ignore nested loops.
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if (op->getParentRegion()->getParentOfType<scf::ForOp>())
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return;
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mapLoopToProcessorIds(op, processorIds, numProcessors);
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});
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}
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};
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} // namespace
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namespace mlir {
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namespace test {
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void registerTestLoopMappingPass() { PassRegistration<TestLoopMappingPass>(); }
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} // namespace test
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} // namespace mlir
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