44 lines
1.7 KiB
ArmAsm
44 lines
1.7 KiB
ArmAsm
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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
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// --------------------------------------------------------------------------//
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// Invalid predicate register
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ld1q {z0.q}, p8/z, [z0.d, x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: ld1q {z0.q}, p8/z, [z0.d, x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld1q {z23.q}, p2/m, [z3.d]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: ld1q {z23.q}, p2/m, [z3.d]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld1q {z21.q}, p2.q, [z5.d]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: ld1q {z21.q}, p2.q, [z5.d]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid order of base & offset
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ld1q {z0.q}, p0/z, [x0, z0.d]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: ld1q {z0.q}, p0/z, [x0, z0.d]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid general purpose register
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ld1q {z0.q}, p0/z, [z0.d, sp]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: ld1q {z0.q}, p0/z, [z0.d, sp]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid suffixes
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ld1q {z0.q}, p0/z, [z2.s]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: ld1q {z0.q}, p0/z, [z2.s]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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