242 lines
14 KiB
C
242 lines
14 KiB
C
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// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
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// REQUIRES: aarch64-registered-target
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// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s
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// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
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// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s
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// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
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// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
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#include <arm_sve.h>
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#ifdef SVE_OVERLOADED_FORMS
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// A simple used,unused... macro, long enough to represent any SVE builtin.
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#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
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#else
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#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
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#endif
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// CHECK-LABEL: @test_svdot_s32(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sdot.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i8> [[OP3:%.*]])
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// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
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//
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// CPP-CHECK-LABEL: @_Z14test_svdot_s32u11__SVInt32_tu10__SVInt8_tS0_(
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// CPP-CHECK-NEXT: entry:
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// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sdot.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i8> [[OP3:%.*]])
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// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
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//
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svint32_t test_svdot_s32(svint32_t op1, svint8_t op2, svint8_t op3)
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{
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return SVE_ACLE_FUNC(svdot,_s32,,)(op1, op2, op3);
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}
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// CHECK-LABEL: @test_svdot_s64(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.sdot.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]])
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// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]
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//
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// CPP-CHECK-LABEL: @_Z14test_svdot_s64u11__SVInt64_tu11__SVInt16_tS0_(
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// CPP-CHECK-NEXT: entry:
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// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.sdot.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]])
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// CPP-CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]
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//
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svint64_t test_svdot_s64(svint64_t op1, svint16_t op2, svint16_t op3)
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{
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return SVE_ACLE_FUNC(svdot,_s64,,)(op1, op2, op3);
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}
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// CHECK-LABEL: @test_svdot_u32(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.udot.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i8> [[OP3:%.*]])
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// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
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//
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// CPP-CHECK-LABEL: @_Z14test_svdot_u32u12__SVUint32_tu11__SVUint8_tS0_(
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// CPP-CHECK-NEXT: entry:
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// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.udot.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i8> [[OP3:%.*]])
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// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
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//
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svuint32_t test_svdot_u32(svuint32_t op1, svuint8_t op2, svuint8_t op3)
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{
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return SVE_ACLE_FUNC(svdot,_u32,,)(op1, op2, op3);
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}
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// CHECK-LABEL: @test_svdot_u64(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.udot.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]])
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// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]
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//
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// CPP-CHECK-LABEL: @_Z14test_svdot_u64u12__SVUint64_tu12__SVUint16_tS0_(
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// CPP-CHECK-NEXT: entry:
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// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.udot.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]])
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// CPP-CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]
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//
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svuint64_t test_svdot_u64(svuint64_t op1, svuint16_t op2, svuint16_t op3)
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{
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return SVE_ACLE_FUNC(svdot,_u64,,)(op1, op2, op3);
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}
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// CHECK-LABEL: @test_svdot_n_s32(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 16 x i8> poison, i8 [[OP3:%.*]], i64 0
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// CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <vscale x 16 x i8> [[DOTSPLATINSERT]], <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
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// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sdot.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i8> [[DOTSPLAT]])
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// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
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//
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// CPP-CHECK-LABEL: @_Z16test_svdot_n_s32u11__SVInt32_tu10__SVInt8_ta(
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// CPP-CHECK-NEXT: entry:
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// CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 16 x i8> poison, i8 [[OP3:%.*]], i64 0
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// CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <vscale x 16 x i8> [[DOTSPLATINSERT]], <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
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// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sdot.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i8> [[DOTSPLAT]])
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// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
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//
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svint32_t test_svdot_n_s32(svint32_t op1, svint8_t op2, int8_t op3)
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{
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return SVE_ACLE_FUNC(svdot,_n_s32,,)(op1, op2, op3);
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}
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// CHECK-LABEL: @test_svdot_n_s64(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 8 x i16> poison, i16 [[OP3:%.*]], i64 0
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// CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <vscale x 8 x i16> [[DOTSPLATINSERT]], <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
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// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.sdot.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[DOTSPLAT]])
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// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]
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//
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// CPP-CHECK-LABEL: @_Z16test_svdot_n_s64u11__SVInt64_tu11__SVInt16_ts(
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// CPP-CHECK-NEXT: entry:
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// CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 8 x i16> poison, i16 [[OP3:%.*]], i64 0
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// CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <vscale x 8 x i16> [[DOTSPLATINSERT]], <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
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// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.sdot.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[DOTSPLAT]])
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// CPP-CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]
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//
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svint64_t test_svdot_n_s64(svint64_t op1, svint16_t op2, int16_t op3)
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{
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return SVE_ACLE_FUNC(svdot,_n_s64,,)(op1, op2, op3);
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}
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// CHECK-LABEL: @test_svdot_n_u32(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 16 x i8> poison, i8 [[OP3:%.*]], i64 0
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// CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <vscale x 16 x i8> [[DOTSPLATINSERT]], <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
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// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.udot.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i8> [[DOTSPLAT]])
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// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
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//
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// CPP-CHECK-LABEL: @_Z16test_svdot_n_u32u12__SVUint32_tu11__SVUint8_th(
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// CPP-CHECK-NEXT: entry:
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// CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 16 x i8> poison, i8 [[OP3:%.*]], i64 0
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// CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <vscale x 16 x i8> [[DOTSPLATINSERT]], <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
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// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.udot.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i8> [[DOTSPLAT]])
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// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
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//
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svuint32_t test_svdot_n_u32(svuint32_t op1, svuint8_t op2, uint8_t op3)
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{
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return SVE_ACLE_FUNC(svdot,_n_u32,,)(op1, op2, op3);
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}
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// CHECK-LABEL: @test_svdot_n_u64(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 8 x i16> poison, i16 [[OP3:%.*]], i64 0
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// CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <vscale x 8 x i16> [[DOTSPLATINSERT]], <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
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// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.udot.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[DOTSPLAT]])
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// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]
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//
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// CPP-CHECK-LABEL: @_Z16test_svdot_n_u64u12__SVUint64_tu12__SVUint16_tt(
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// CPP-CHECK-NEXT: entry:
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// CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 8 x i16> poison, i16 [[OP3:%.*]], i64 0
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// CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <vscale x 8 x i16> [[DOTSPLATINSERT]], <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
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// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.udot.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[DOTSPLAT]])
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// CPP-CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]
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//
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svuint64_t test_svdot_n_u64(svuint64_t op1, svuint16_t op2, uint16_t op3)
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{
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return SVE_ACLE_FUNC(svdot,_n_u64,,)(op1, op2, op3);
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}
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// CHECK-LABEL: @test_svdot_lane_s32(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sdot.lane.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i8> [[OP3:%.*]], i32 0)
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// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
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//
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// CPP-CHECK-LABEL: @_Z19test_svdot_lane_s32u11__SVInt32_tu10__SVInt8_tS0_(
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// CPP-CHECK-NEXT: entry:
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// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sdot.lane.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i8> [[OP3:%.*]], i32 0)
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// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
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//
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svint32_t test_svdot_lane_s32(svint32_t op1, svint8_t op2, svint8_t op3)
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{
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return SVE_ACLE_FUNC(svdot_lane,_s32,,)(op1, op2, op3, 0);
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}
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// CHECK-LABEL: @test_svdot_lane_s32_1(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sdot.lane.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i8> [[OP3:%.*]], i32 3)
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// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
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//
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// CPP-CHECK-LABEL: @_Z21test_svdot_lane_s32_1u11__SVInt32_tu10__SVInt8_tS0_(
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// CPP-CHECK-NEXT: entry:
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// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sdot.lane.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i8> [[OP3:%.*]], i32 3)
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// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
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//
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svint32_t test_svdot_lane_s32_1(svint32_t op1, svint8_t op2, svint8_t op3)
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{
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return SVE_ACLE_FUNC(svdot_lane,_s32,,)(op1, op2, op3, 3);
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}
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// CHECK-LABEL: @test_svdot_lane_s64(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.sdot.lane.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]], i32 0)
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// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]
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//
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// CPP-CHECK-LABEL: @_Z19test_svdot_lane_s64u11__SVInt64_tu11__SVInt16_tS0_(
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// CPP-CHECK-NEXT: entry:
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// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.sdot.lane.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]], i32 0)
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// CPP-CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]
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//
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svint64_t test_svdot_lane_s64(svint64_t op1, svint16_t op2, svint16_t op3)
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{
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return SVE_ACLE_FUNC(svdot_lane,_s64,,)(op1, op2, op3, 0);
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}
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// CHECK-LABEL: @test_svdot_lane_s64_1(
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// CHECK-NEXT: entry:
|
||
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|
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.sdot.lane.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]], i32 1)
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||
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// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]
|
||
|
|
//
|
||
|
|
// CPP-CHECK-LABEL: @_Z21test_svdot_lane_s64_1u11__SVInt64_tu11__SVInt16_tS0_(
|
||
|
|
// CPP-CHECK-NEXT: entry:
|
||
|
|
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.sdot.lane.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]], i32 1)
|
||
|
|
// CPP-CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]
|
||
|
|
//
|
||
|
|
svint64_t test_svdot_lane_s64_1(svint64_t op1, svint16_t op2, svint16_t op3)
|
||
|
|
{
|
||
|
|
return SVE_ACLE_FUNC(svdot_lane,_s64,,)(op1, op2, op3, 1);
|
||
|
|
}
|
||
|
|
|
||
|
|
// CHECK-LABEL: @test_svdot_lane_u32(
|
||
|
|
// CHECK-NEXT: entry:
|
||
|
|
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.udot.lane.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i8> [[OP3:%.*]], i32 3)
|
||
|
|
// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
|
||
|
|
//
|
||
|
|
// CPP-CHECK-LABEL: @_Z19test_svdot_lane_u32u12__SVUint32_tu11__SVUint8_tS0_(
|
||
|
|
// CPP-CHECK-NEXT: entry:
|
||
|
|
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.udot.lane.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i8> [[OP3:%.*]], i32 3)
|
||
|
|
// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
|
||
|
|
//
|
||
|
|
svuint32_t test_svdot_lane_u32(svuint32_t op1, svuint8_t op2, svuint8_t op3)
|
||
|
|
{
|
||
|
|
return SVE_ACLE_FUNC(svdot_lane,_u32,,)(op1, op2, op3, 3);
|
||
|
|
}
|
||
|
|
|
||
|
|
// CHECK-LABEL: @test_svdot_lane_u64(
|
||
|
|
// CHECK-NEXT: entry:
|
||
|
|
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.udot.lane.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]], i32 1)
|
||
|
|
// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]
|
||
|
|
//
|
||
|
|
// CPP-CHECK-LABEL: @_Z19test_svdot_lane_u64u12__SVUint64_tu12__SVUint16_tS0_(
|
||
|
|
// CPP-CHECK-NEXT: entry:
|
||
|
|
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.udot.lane.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]], i32 1)
|
||
|
|
// CPP-CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]
|
||
|
|
//
|
||
|
|
svuint64_t test_svdot_lane_u64(svuint64_t op1, svuint16_t op2, svuint16_t op3)
|
||
|
|
{
|
||
|
|
return SVE_ACLE_FUNC(svdot_lane,_u64,,)(op1, op2, op3, 1);
|
||
|
|
}
|