98 lines
3.3 KiB
C
98 lines
3.3 KiB
C
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//===-- SILowerI1Copies.h --------------------------------------*- C++ -*--===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// Interface definition of the PhiLoweringHelper class that implements lane
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/// mask merging algorithm for divergent i1 phis.
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//
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//===----------------------------------------------------------------------===//
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#include "GCNSubtarget.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachinePostDominators.h"
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#include "llvm/CodeGen/MachineSSAUpdater.h"
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namespace llvm {
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/// Incoming for lane maks phi as machine instruction, incoming register \p Reg
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/// and incoming block \p Block are taken from machine instruction.
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/// \p UpdatedReg (if valid) is \p Reg lane mask merged with another lane mask.
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struct Incoming {
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Register Reg;
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MachineBasicBlock *Block;
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Register UpdatedReg;
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Incoming(Register Reg, MachineBasicBlock *Block, Register UpdatedReg)
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: Reg(Reg), Block(Block), UpdatedReg(UpdatedReg) {}
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};
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Register createLaneMaskReg(MachineRegisterInfo *MRI, Register LaneMaskRegAttrs);
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class PhiLoweringHelper {
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public:
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PhiLoweringHelper(MachineFunction *MF, MachineDominatorTree *DT,
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MachinePostDominatorTree *PDT);
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virtual ~PhiLoweringHelper() = default;
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protected:
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bool IsWave32 = false;
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MachineFunction *MF = nullptr;
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MachineDominatorTree *DT = nullptr;
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MachinePostDominatorTree *PDT = nullptr;
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MachineRegisterInfo *MRI = nullptr;
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const GCNSubtarget *ST = nullptr;
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const SIInstrInfo *TII = nullptr;
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Register LaneMaskRegAttrs;
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#ifndef NDEBUG
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DenseSet<Register> PhiRegisters;
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#endif
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Register ExecReg;
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unsigned MovOp;
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unsigned AndOp;
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unsigned OrOp;
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unsigned XorOp;
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unsigned AndN2Op;
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unsigned OrN2Op;
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public:
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bool lowerPhis();
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bool isConstantLaneMask(Register Reg, bool &Val) const;
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MachineBasicBlock::iterator
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getSaluInsertionAtEnd(MachineBasicBlock &MBB) const;
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void initializeLaneMaskRegisterAttributes(Register LaneMask) {
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LaneMaskRegAttrs = LaneMask;
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}
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bool isLaneMaskReg(Register Reg) const {
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return TII->getRegisterInfo().isSGPRReg(*MRI, Reg) &&
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TII->getRegisterInfo().getRegSizeInBits(Reg, *MRI) ==
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ST->getWavefrontSize();
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}
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// Helpers from lowerPhis that are different between sdag and global-isel.
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virtual void markAsLaneMask(Register DstReg) const = 0;
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virtual void getCandidatesForLowering(
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SmallVectorImpl<MachineInstr *> &Vreg1Phis) const = 0;
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virtual void
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collectIncomingValuesFromPhi(const MachineInstr *MI,
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SmallVectorImpl<Incoming> &Incomings) const = 0;
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virtual void replaceDstReg(Register NewReg, Register OldReg,
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MachineBasicBlock *MBB) = 0;
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virtual void buildMergeLaneMasks(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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const DebugLoc &DL, Register DstReg,
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Register PrevReg, Register CurReg) = 0;
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virtual void constrainIncomingRegisterTakenAsIs(Incoming &In) = 0;
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};
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} // end namespace llvm
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