49 lines
2.2 KiB
LLVM
49 lines
2.2 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple aarch64-none-linux-gnu | FileCheck %s
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define <16 x i8> @test_combine_v8i16_to_v16i8(<8 x i16> %x, <8 x i16> %y) {
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; CHECK-LABEL: test_combine_v8i16_to_v16i8:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: movi v2.2d, #0000000000000000
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; CHECK-NEXT: raddhn v0.8b, v0.8h, v2.8h
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; CHECK-NEXT: raddhn2 v0.16b, v1.8h, v2.8h
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; CHECK-NEXT: ret
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entry:
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%res = call <8 x i8> @llvm.aarch64.neon.rshrn.v8i8(<8 x i16> %x, i32 8)
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%res2 = call <8 x i8> @llvm.aarch64.neon.rshrn.v8i8(<8 x i16> %y, i32 8)
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%shuffle = shufflevector <8 x i8> %res, <8 x i8> %res2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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ret <16 x i8> %shuffle
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}
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define <8 x i16> @test_combine_v4i32_to_v8i16(<4 x i32> %x, <4 x i32> %y) {
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; CHECK-LABEL: test_combine_v4i32_to_v8i16:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: movi v2.2d, #0000000000000000
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; CHECK-NEXT: raddhn v0.4h, v0.4s, v2.4s
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; CHECK-NEXT: raddhn2 v0.8h, v1.4s, v2.4s
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; CHECK-NEXT: ret
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entry:
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%res = call <4 x i16> @llvm.aarch64.neon.rshrn.v4i16(<4 x i32> %x, i32 16)
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%res2 = call <4 x i16> @llvm.aarch64.neon.rshrn.v4i16(<4 x i32> %y, i32 16)
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%shuffle = shufflevector <4 x i16> %res, <4 x i16> %res2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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ret <8 x i16> %shuffle
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}
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define <4 x i32> @test_combine_v2i64_to_v4i32(<2 x i64> %x, <2 x i64> %y) {
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; CHECK-LABEL: test_combine_v2i64_to_v4i32:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: movi v2.2d, #0000000000000000
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; CHECK-NEXT: raddhn v0.2s, v0.2d, v2.2d
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; CHECK-NEXT: raddhn2 v0.4s, v1.2d, v2.2d
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; CHECK-NEXT: ret
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entry:
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%res = call <2 x i32> @llvm.aarch64.neon.rshrn.v2i32(<2 x i64> %x, i32 32)
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%res2 = call <2 x i32> @llvm.aarch64.neon.rshrn.v2i32(<2 x i64> %y, i32 32)
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%shuffle = shufflevector <2 x i32> %res, <2 x i32> %res2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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ret <4 x i32> %shuffle
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}
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declare <8 x i8> @llvm.aarch64.neon.rshrn.v8i8(<8 x i16>, i32)
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declare <4 x i16> @llvm.aarch64.neon.rshrn.v4i16(<4 x i32>, i32)
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declare <2 x i32> @llvm.aarch64.neon.rshrn.v2i32(<2 x i64>, i32)
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