108 lines
3.3 KiB
LLVM
108 lines
3.3 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2-aes,+sve2-sha3,+sve2-sm4 < %s | FileCheck %s
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;
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; AESD
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;
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define <vscale x 16 x i8> @aesd_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
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; CHECK-LABEL: aesd_i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: aesd z0.b, z0.b, z1.b
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; CHECK-NEXT: ret
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%out = call <vscale x 16 x i8> @llvm.aarch64.sve.aesd(<vscale x 16 x i8> %a,
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<vscale x 16 x i8> %b)
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ret <vscale x 16 x i8> %out
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}
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;
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; AESIMC
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;
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define <vscale x 16 x i8> @aesimc_i8(<vscale x 16 x i8> %a) {
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; CHECK-LABEL: aesimc_i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: aesimc z0.b, z0.b
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; CHECK-NEXT: ret
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%out = call <vscale x 16 x i8> @llvm.aarch64.sve.aesimc(<vscale x 16 x i8> %a)
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ret <vscale x 16 x i8> %out
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}
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;
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; AESE
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;
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define <vscale x 16 x i8> @aese_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
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; CHECK-LABEL: aese_i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: aese z0.b, z0.b, z1.b
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; CHECK-NEXT: ret
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%out = call <vscale x 16 x i8> @llvm.aarch64.sve.aese(<vscale x 16 x i8> %a,
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<vscale x 16 x i8> %b)
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ret <vscale x 16 x i8> %out
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}
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;
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; AESMC
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;
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define <vscale x 16 x i8> @aesmc_i8(<vscale x 16 x i8> %a) {
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; CHECK-LABEL: aesmc_i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: aesmc z0.b, z0.b
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; CHECK-NEXT: ret
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%out = call <vscale x 16 x i8> @llvm.aarch64.sve.aesmc(<vscale x 16 x i8> %a)
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ret <vscale x 16 x i8> %out
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}
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;
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; RAX1
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;
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define <vscale x 2 x i64> @rax1_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
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; CHECK-LABEL: rax1_i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: rax1 z0.d, z0.d, z1.d
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; CHECK-NEXT: ret
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%out = call <vscale x 2 x i64> @llvm.aarch64.sve.rax1(<vscale x 2 x i64> %a,
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<vscale x 2 x i64> %b)
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ret <vscale x 2 x i64> %out
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}
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;
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; SM4E
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;
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define <vscale x 4 x i32> @sm4e_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
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; CHECK-LABEL: sm4e_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sm4e z0.s, z0.s, z1.s
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; CHECK-NEXT: ret
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%out = call <vscale x 4 x i32> @llvm.aarch64.sve.sm4e(<vscale x 4 x i32> %a,
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<vscale x 4 x i32> %b)
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ret <vscale x 4 x i32> %out
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}
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;
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; SM4EKEY
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;
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define <vscale x 4 x i32> @sm4ekey_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
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; CHECK-LABEL: sm4ekey_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sm4ekey z0.s, z0.s, z1.s
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; CHECK-NEXT: ret
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%out = call <vscale x 4 x i32> @llvm.aarch64.sve.sm4ekey(<vscale x 4 x i32> %a,
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<vscale x 4 x i32> %b)
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ret <vscale x 4 x i32> %out
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}
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declare <vscale x 16 x i8> @llvm.aarch64.sve.aesd(<vscale x 16 x i8>, <vscale x 16 x i8>)
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declare <vscale x 16 x i8> @llvm.aarch64.sve.aesimc(<vscale x 16 x i8>)
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declare <vscale x 16 x i8> @llvm.aarch64.sve.aese(<vscale x 16 x i8>, <vscale x 16 x i8>)
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declare <vscale x 16 x i8> @llvm.aarch64.sve.aesmc(<vscale x 16 x i8>)
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declare <vscale x 2 x i64> @llvm.aarch64.sve.rax1(<vscale x 2 x i64>, <vscale x 2 x i64>)
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declare <vscale x 4 x i32> @llvm.aarch64.sve.sm4e(<vscale x 4 x i32>, <vscale x 4 x i32>)
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declare <vscale x 4 x i32> @llvm.aarch64.sve.sm4ekey(<vscale x 4 x i32>, <vscale x 4 x i32>)
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