180 lines
8.1 KiB
LLVM
180 lines
8.1 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck --check-prefix=VARIANT0 %s
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; RUN: llc -mtriple=amdgcn -mattr=+auto-waitcnt-before-barrier -verify-machineinstrs < %s | FileCheck --check-prefix=VARIANT1 %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck --check-prefix=VARIANT2 %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=+auto-waitcnt-before-barrier -verify-machineinstrs < %s | FileCheck --check-prefix=VARIANT3 %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck --check-prefix=VARIANT4 %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+auto-waitcnt-before-barrier -verify-machineinstrs < %s | FileCheck --check-prefix=VARIANT5 %s
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; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck --check-prefix=VARIANT6 %s
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define amdgpu_kernel void @test_barrier(ptr addrspace(1) %out, i32 %size) #0 {
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; VARIANT0-LABEL: test_barrier:
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; VARIANT0: ; %bb.0: ; %entry
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; VARIANT0-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
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; VARIANT0-NEXT: s_load_dword s0, s[0:1], 0xb
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; VARIANT0-NEXT: s_mov_b32 s7, 0xf000
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; VARIANT0-NEXT: s_mov_b32 s6, 0
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; VARIANT0-NEXT: v_lshlrev_b32_e32 v1, 2, v0
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; VARIANT0-NEXT: v_mov_b32_e32 v2, 0
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; VARIANT0-NEXT: v_not_b32_e32 v3, v0
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; VARIANT0-NEXT: s_waitcnt lgkmcnt(0)
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; VARIANT0-NEXT: buffer_store_dword v0, v[1:2], s[4:7], 0 addr64
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; VARIANT0-NEXT: s_waitcnt vmcnt(0) expcnt(0)
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; VARIANT0-NEXT: s_barrier
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; VARIANT0-NEXT: v_add_i32_e32 v3, vcc, s0, v3
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; VARIANT0-NEXT: v_ashrrev_i32_e32 v4, 31, v3
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; VARIANT0-NEXT: v_lshl_b64 v[3:4], v[3:4], 2
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; VARIANT0-NEXT: buffer_load_dword v0, v[3:4], s[4:7], 0 addr64
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; VARIANT0-NEXT: s_waitcnt vmcnt(0)
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; VARIANT0-NEXT: buffer_store_dword v0, v[1:2], s[4:7], 0 addr64
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; VARIANT0-NEXT: s_endpgm
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;
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; VARIANT1-LABEL: test_barrier:
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; VARIANT1: ; %bb.0: ; %entry
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; VARIANT1-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
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; VARIANT1-NEXT: s_load_dword s0, s[0:1], 0xb
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; VARIANT1-NEXT: s_mov_b32 s7, 0xf000
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; VARIANT1-NEXT: s_mov_b32 s6, 0
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; VARIANT1-NEXT: v_lshlrev_b32_e32 v1, 2, v0
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; VARIANT1-NEXT: v_mov_b32_e32 v2, 0
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; VARIANT1-NEXT: v_not_b32_e32 v3, v0
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; VARIANT1-NEXT: s_waitcnt lgkmcnt(0)
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; VARIANT1-NEXT: buffer_store_dword v0, v[1:2], s[4:7], 0 addr64
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; VARIANT1-NEXT: s_barrier
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; VARIANT1-NEXT: v_add_i32_e32 v3, vcc, s0, v3
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; VARIANT1-NEXT: v_ashrrev_i32_e32 v4, 31, v3
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; VARIANT1-NEXT: v_lshl_b64 v[3:4], v[3:4], 2
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; VARIANT1-NEXT: s_waitcnt expcnt(0)
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; VARIANT1-NEXT: buffer_load_dword v0, v[3:4], s[4:7], 0 addr64
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; VARIANT1-NEXT: s_waitcnt vmcnt(0)
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; VARIANT1-NEXT: buffer_store_dword v0, v[1:2], s[4:7], 0 addr64
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; VARIANT1-NEXT: s_endpgm
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;
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; VARIANT2-LABEL: test_barrier:
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; VARIANT2: ; %bb.0: ; %entry
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; VARIANT2-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
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; VARIANT2-NEXT: s_load_dword s4, s[0:1], 0x2c
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; VARIANT2-NEXT: v_lshlrev_b32_e32 v2, 2, v0
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; VARIANT2-NEXT: s_waitcnt lgkmcnt(0)
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; VARIANT2-NEXT: global_store_dword v2, v0, s[2:3]
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; VARIANT2-NEXT: v_xad_u32 v0, v0, -1, s4
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; VARIANT2-NEXT: v_ashrrev_i32_e32 v1, 31, v0
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; VARIANT2-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1]
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; VARIANT2-NEXT: v_mov_b32_e32 v3, s3
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; VARIANT2-NEXT: v_add_co_u32_e32 v0, vcc, s2, v0
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; VARIANT2-NEXT: v_addc_co_u32_e32 v1, vcc, v3, v1, vcc
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; VARIANT2-NEXT: s_waitcnt vmcnt(0)
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; VARIANT2-NEXT: s_barrier
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; VARIANT2-NEXT: global_load_dword v0, v[0:1], off
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; VARIANT2-NEXT: s_waitcnt vmcnt(0)
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; VARIANT2-NEXT: global_store_dword v2, v0, s[2:3]
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; VARIANT2-NEXT: s_endpgm
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;
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; VARIANT3-LABEL: test_barrier:
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; VARIANT3: ; %bb.0: ; %entry
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; VARIANT3-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
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; VARIANT3-NEXT: s_load_dword s4, s[0:1], 0x2c
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; VARIANT3-NEXT: v_lshlrev_b32_e32 v2, 2, v0
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; VARIANT3-NEXT: s_waitcnt lgkmcnt(0)
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; VARIANT3-NEXT: global_store_dword v2, v0, s[2:3]
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; VARIANT3-NEXT: v_xad_u32 v0, v0, -1, s4
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; VARIANT3-NEXT: v_ashrrev_i32_e32 v1, 31, v0
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; VARIANT3-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1]
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; VARIANT3-NEXT: v_mov_b32_e32 v3, s3
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; VARIANT3-NEXT: v_add_co_u32_e32 v0, vcc, s2, v0
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; VARIANT3-NEXT: v_addc_co_u32_e32 v1, vcc, v3, v1, vcc
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; VARIANT3-NEXT: s_barrier
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; VARIANT3-NEXT: global_load_dword v0, v[0:1], off
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; VARIANT3-NEXT: s_waitcnt vmcnt(0)
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; VARIANT3-NEXT: global_store_dword v2, v0, s[2:3]
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; VARIANT3-NEXT: s_endpgm
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;
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; VARIANT4-LABEL: test_barrier:
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; VARIANT4: ; %bb.0: ; %entry
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; VARIANT4-NEXT: s_load_b96 s[0:2], s[0:1], 0x24
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; VARIANT4-NEXT: v_lshlrev_b32_e32 v3, 2, v0
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; VARIANT4-NEXT: s_wait_kmcnt 0x0
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; VARIANT4-NEXT: v_xad_u32 v1, v0, -1, s2
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; VARIANT4-NEXT: global_store_b32 v3, v0, s[0:1]
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; VARIANT4-NEXT: s_wait_storecnt 0x0
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; VARIANT4-NEXT: s_barrier_signal -1
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; VARIANT4-NEXT: s_barrier_wait -1
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; VARIANT4-NEXT: v_ashrrev_i32_e32 v2, 31, v1
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; VARIANT4-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
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; VARIANT4-NEXT: v_lshlrev_b64_e32 v[1:2], 2, v[1:2]
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; VARIANT4-NEXT: v_add_co_u32 v1, vcc_lo, s0, v1
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; VARIANT4-NEXT: s_delay_alu instid0(VALU_DEP_2)
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; VARIANT4-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
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; VARIANT4-NEXT: global_load_b32 v0, v[1:2], off
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; VARIANT4-NEXT: s_wait_loadcnt 0x0
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; VARIANT4-NEXT: global_store_b32 v3, v0, s[0:1]
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; VARIANT4-NEXT: s_nop 0
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; VARIANT4-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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; VARIANT4-NEXT: s_endpgm
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;
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; VARIANT5-LABEL: test_barrier:
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; VARIANT5: ; %bb.0: ; %entry
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; VARIANT5-NEXT: s_load_b96 s[0:2], s[0:1], 0x24
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; VARIANT5-NEXT: v_lshlrev_b32_e32 v3, 2, v0
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; VARIANT5-NEXT: s_wait_kmcnt 0x0
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; VARIANT5-NEXT: v_xad_u32 v1, v0, -1, s2
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; VARIANT5-NEXT: global_store_b32 v3, v0, s[0:1]
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; VARIANT5-NEXT: s_barrier_signal -1
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; VARIANT5-NEXT: s_barrier_wait -1
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; VARIANT5-NEXT: v_ashrrev_i32_e32 v2, 31, v1
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; VARIANT5-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
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; VARIANT5-NEXT: v_lshlrev_b64_e32 v[1:2], 2, v[1:2]
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; VARIANT5-NEXT: v_add_co_u32 v1, vcc_lo, s0, v1
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; VARIANT5-NEXT: s_delay_alu instid0(VALU_DEP_2)
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; VARIANT5-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
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; VARIANT5-NEXT: global_load_b32 v0, v[1:2], off
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; VARIANT5-NEXT: s_wait_loadcnt 0x0
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; VARIANT5-NEXT: global_store_b32 v3, v0, s[0:1]
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; VARIANT5-NEXT: s_nop 0
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; VARIANT5-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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; VARIANT5-NEXT: s_endpgm
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;
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; VARIANT6-LABEL: test_barrier:
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; VARIANT6: ; %bb.0: ; %entry
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; VARIANT6-NEXT: s_load_b96 s[0:2], s[0:1], 0x24
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; VARIANT6-NEXT: v_lshlrev_b32_e32 v5, 2, v0
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; VARIANT6-NEXT: s_wait_kmcnt 0x0
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; VARIANT6-NEXT: s_sub_co_i32 s2, s2, 1
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; VARIANT6-NEXT: v_dual_mov_b32 v4, s1 :: v_dual_mov_b32 v3, s0
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; VARIANT6-NEXT: v_sub_nc_u32_e32 v1, s2, v0
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; VARIANT6-NEXT: global_store_b32 v5, v0, s[0:1]
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; VARIANT6-NEXT: s_wait_storecnt 0x0
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; VARIANT6-NEXT: s_barrier_signal -1
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; VARIANT6-NEXT: s_barrier_wait -1
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; VARIANT6-NEXT: v_ashrrev_i32_e32 v2, 31, v1
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; VARIANT6-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
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; VARIANT6-NEXT: v_lshlrev_b64_e32 v[1:2], 2, v[1:2]
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; VARIANT6-NEXT: v_add_co_u32 v1, vcc_lo, v3, v1
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; VARIANT6-NEXT: s_delay_alu instid0(VALU_DEP_2)
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; VARIANT6-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
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; VARIANT6-NEXT: global_load_b32 v0, v[1:2], off
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; VARIANT6-NEXT: s_wait_loadcnt 0x0
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; VARIANT6-NEXT: global_store_b32 v5, v0, s[0:1]
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; VARIANT6-NEXT: s_nop 0
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; VARIANT6-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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; VARIANT6-NEXT: s_endpgm
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entry:
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%tmp = call i32 @llvm.amdgcn.workitem.id.x()
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%tmp1 = getelementptr i32, ptr addrspace(1) %out, i32 %tmp
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store i32 %tmp, ptr addrspace(1) %tmp1
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call void @llvm.amdgcn.s.barrier()
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%tmp3 = sub i32 %size, 1
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%tmp4 = sub i32 %tmp3, %tmp
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%tmp5 = getelementptr i32, ptr addrspace(1) %out, i32 %tmp4
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%tmp6 = load i32, ptr addrspace(1) %tmp5
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store i32 %tmp6, ptr addrspace(1) %tmp1
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ret void
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}
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declare void @llvm.amdgcn.s.barrier() #1
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declare i32 @llvm.amdgcn.workitem.id.x() #2
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attributes #0 = { nounwind }
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attributes #1 = { convergent nounwind }
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attributes #2 = { nounwind readnone }
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