bolt/deps/llvm-18.1.8/llvm/test/CodeGen/Hexagon/vect/vect-vsubb-1.ll

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2025-02-14 19:21:04 +01:00
; RUN: llc -march=hexagon < %s | FileCheck %s
; CHECK: vsubub
define <4 x i8> @t_i4x8(<4 x i8> %a, <4 x i8> %b) nounwind {
entry:
%0 = sub <4 x i8> %a, %b
ret <4 x i8> %0
}