813 lines
22 KiB
Text
813 lines
22 KiB
Text
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=riscv64 -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
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# RUN: | FileCheck -check-prefix=RV64I %s
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---
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name: add_i8_zeroext
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $x10, $x11
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; RV64I-LABEL: name: add_i8_zeroext
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; RV64I: liveins: $x10, $x11
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; RV64I-NEXT: {{ $}}
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; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
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; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
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; RV64I-NEXT: [[ADDW:%[0-9]+]]:gpr = ADDW [[COPY]], [[COPY1]]
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; RV64I-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[ADDW]], 255
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; RV64I-NEXT: $x10 = COPY [[ANDI]]
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; RV64I-NEXT: PseudoRET implicit $x10
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%2:gprb(s64) = COPY $x10
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%3:gprb(s64) = COPY $x11
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%6:gprb(s32) = G_TRUNC %2(s64)
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%7:gprb(s32) = G_TRUNC %3(s64)
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%8:gprb(s32) = G_ADD %6, %7
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%9:gprb(s64) = G_CONSTANT i64 255
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%10:gprb(s64) = G_ANYEXT %8(s32)
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%5:gprb(s64) = G_AND %10, %9
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$x10 = COPY %5(s64)
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PseudoRET implicit $x10
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...
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---
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name: add_i16_signext
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $x10, $x11
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; RV64I-LABEL: name: add_i16_signext
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; RV64I: liveins: $x10, $x11
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; RV64I-NEXT: {{ $}}
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; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
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; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
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; RV64I-NEXT: [[ADDW:%[0-9]+]]:gpr = ADDW [[COPY]], [[COPY1]]
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; RV64I-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[ADDW]], 48
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; RV64I-NEXT: [[SRAI:%[0-9]+]]:gpr = SRAI [[SLLI]], 48
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; RV64I-NEXT: $x10 = COPY [[SRAI]]
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; RV64I-NEXT: PseudoRET implicit $x10
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%2:gprb(s64) = COPY $x10
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%3:gprb(s64) = COPY $x11
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%6:gprb(s32) = G_TRUNC %2(s64)
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%7:gprb(s32) = G_TRUNC %3(s64)
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%8:gprb(s32) = G_ADD %6, %7
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%9:gprb(s64) = G_ANYEXT %8(s32)
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%11:gprb(s64) = G_CONSTANT i64 48
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%10:gprb(s64) = G_SHL %9, %11(s64)
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%5:gprb(s64) = G_ASHR %10, %11(s64)
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$x10 = COPY %5(s64)
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PseudoRET implicit $x10
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...
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---
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name: add_i16_zeroext
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $x10, $x11
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; RV64I-LABEL: name: add_i16_zeroext
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; RV64I: liveins: $x10, $x11
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; RV64I-NEXT: {{ $}}
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; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
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; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
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; RV64I-NEXT: [[ADDW:%[0-9]+]]:gpr = ADDW [[COPY]], [[COPY1]]
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; RV64I-NEXT: [[LUI:%[0-9]+]]:gpr = LUI 16
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; RV64I-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[LUI]], -1
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; RV64I-NEXT: [[AND:%[0-9]+]]:gpr = AND [[ADDW]], [[ADDIW]]
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; RV64I-NEXT: $x10 = COPY [[AND]]
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; RV64I-NEXT: PseudoRET implicit $x10
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%2:gprb(s64) = COPY $x10
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%3:gprb(s64) = COPY $x11
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%6:gprb(s32) = G_TRUNC %2(s64)
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%7:gprb(s32) = G_TRUNC %3(s64)
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%8:gprb(s32) = G_ADD %6, %7
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%9:gprb(s64) = G_CONSTANT i64 65535
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%10:gprb(s64) = G_ANYEXT %8(s32)
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%5:gprb(s64) = G_AND %10, %9
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$x10 = COPY %5(s64)
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PseudoRET implicit $x10
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...
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---
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name: add_i32
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $x10, $x11
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; RV64I-LABEL: name: add_i32
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; RV64I: liveins: $x10, $x11
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; RV64I-NEXT: {{ $}}
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; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
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; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
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; RV64I-NEXT: [[ADDW:%[0-9]+]]:gpr = ADDW [[COPY]], [[COPY1]]
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; RV64I-NEXT: $x10 = COPY [[ADDW]]
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; RV64I-NEXT: PseudoRET implicit $x10
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%0:gprb(s64) = COPY $x10
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%1:gprb(s32) = G_TRUNC %0(s64)
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%2:gprb(s64) = COPY $x11
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%3:gprb(s32) = G_TRUNC %2(s64)
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%4:gprb(s32) = G_ADD %1, %3
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%5:gprb(s64) = G_ANYEXT %4(s32)
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$x10 = COPY %5(s64)
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PseudoRET implicit $x10
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...
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---
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name: addi_i32
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $x10
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; RV64I-LABEL: name: addi_i32
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; RV64I: liveins: $x10
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; RV64I-NEXT: {{ $}}
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; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
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; RV64I-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[COPY]], 1234
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; RV64I-NEXT: $x10 = COPY [[ADDIW]]
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; RV64I-NEXT: PseudoRET implicit $x10
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%0:gprb(s64) = COPY $x10
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%1:gprb(s32) = G_TRUNC %0(s64)
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%2:gprb(s32) = G_CONSTANT i32 1234
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%3:gprb(s32) = G_ADD %1, %2
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%4:gprb(s64) = G_ANYEXT %3(s32)
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$x10 = COPY %4(s64)
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PseudoRET implicit $x10
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...
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---
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name: sub_i32
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $x10, $x11
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; RV64I-LABEL: name: sub_i32
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; RV64I: liveins: $x10, $x11
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; RV64I-NEXT: {{ $}}
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; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
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; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
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; RV64I-NEXT: [[SUBW:%[0-9]+]]:gpr = SUBW [[COPY]], [[COPY1]]
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; RV64I-NEXT: $x10 = COPY [[SUBW]]
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; RV64I-NEXT: PseudoRET implicit $x10
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%0:gprb(s64) = COPY $x10
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%1:gprb(s32) = G_TRUNC %0(s64)
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%2:gprb(s64) = COPY $x11
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%3:gprb(s32) = G_TRUNC %2(s64)
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%4:gprb(s32) = G_SUB %1, %3
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%5:gprb(s64) = G_ANYEXT %4(s32)
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$x10 = COPY %5(s64)
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PseudoRET implicit $x10
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...
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---
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name: subi_i32
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $x10
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; RV64I-LABEL: name: subi_i32
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; RV64I: liveins: $x10
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; RV64I-NEXT: {{ $}}
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; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
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; RV64I-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[COPY]], 1234
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; RV64I-NEXT: $x10 = COPY [[ADDIW]]
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; RV64I-NEXT: PseudoRET implicit $x10
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%0:gprb(s64) = COPY $x10
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%1:gprb(s32) = G_TRUNC %0(s64)
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%2:gprb(s32) = G_CONSTANT i32 -1234
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%3:gprb(s32) = G_SUB %1, %2
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%4:gprb(s64) = G_ANYEXT %3(s32)
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$x10 = COPY %4(s64)
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PseudoRET implicit $x10
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...
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---
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name: sll_i32
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $x10, $x11
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; RV64I-LABEL: name: sll_i32
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; RV64I: liveins: $x10, $x11
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; RV64I-NEXT: {{ $}}
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; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
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; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
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; RV64I-NEXT: [[SLLW:%[0-9]+]]:gpr = SLLW [[COPY]], [[COPY1]]
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; RV64I-NEXT: $x10 = COPY [[SLLW]]
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; RV64I-NEXT: PseudoRET implicit $x10
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%0:gprb(s64) = COPY $x10
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%1:gprb(s32) = G_TRUNC %0(s64)
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%2:gprb(s64) = COPY $x11
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%3:gprb(s32) = G_TRUNC %2(s64)
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%4:gprb(s32) = G_SHL %1, %3(s32)
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%5:gprb(s64) = G_ANYEXT %4(s32)
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$x10 = COPY %5(s64)
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PseudoRET implicit $x10
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...
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---
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name: slli_i32
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $x10
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; RV64I-LABEL: name: slli_i32
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; RV64I: liveins: $x10
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; RV64I-NEXT: {{ $}}
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; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
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; RV64I-NEXT: [[SLLIW:%[0-9]+]]:gpr = SLLIW [[COPY]], 31
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; RV64I-NEXT: $x10 = COPY [[SLLIW]]
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; RV64I-NEXT: PseudoRET implicit $x10
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%0:gprb(s64) = COPY $x10
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%1:gprb(s32) = G_TRUNC %0(s64)
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%2:gprb(s64) = G_CONSTANT i64 31
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%3:gprb(s32) = G_SHL %1, %2(s64)
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%4:gprb(s64) = G_ANYEXT %3(s32)
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$x10 = COPY %4(s64)
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PseudoRET implicit $x10
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...
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---
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name: sra_i32
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $x10, $x11
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; RV64I-LABEL: name: sra_i32
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; RV64I: liveins: $x10, $x11
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; RV64I-NEXT: {{ $}}
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; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
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; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
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; RV64I-NEXT: [[SRAW:%[0-9]+]]:gpr = SRAW [[COPY]], [[COPY1]]
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; RV64I-NEXT: $x10 = COPY [[SRAW]]
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; RV64I-NEXT: PseudoRET implicit $x10
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%0:gprb(s64) = COPY $x10
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%1:gprb(s32) = G_TRUNC %0(s64)
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%2:gprb(s64) = COPY $x11
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%3:gprb(s32) = G_TRUNC %2(s64)
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%4:gprb(s32) = G_ASHR %1, %3(s32)
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%5:gprb(s64) = G_ANYEXT %4(s32)
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$x10 = COPY %5(s64)
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PseudoRET implicit $x10
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...
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---
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name: srai_i32
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $x10
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; RV64I-LABEL: name: srai_i32
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; RV64I: liveins: $x10
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; RV64I-NEXT: {{ $}}
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; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
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; RV64I-NEXT: [[SRAIW:%[0-9]+]]:gpr = SRAIW [[COPY]], 31
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; RV64I-NEXT: $x10 = COPY [[SRAIW]]
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; RV64I-NEXT: PseudoRET implicit $x10
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%0:gprb(s64) = COPY $x10
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%1:gprb(s32) = G_TRUNC %0(s64)
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%2:gprb(s64) = G_CONSTANT i64 31
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%3:gprb(s32) = G_ASHR %1, %2(s64)
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%4:gprb(s64) = G_ANYEXT %3(s32)
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$x10 = COPY %4(s64)
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PseudoRET implicit $x10
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...
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---
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name: srl_i32
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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|
|
body: |
|
||
|
|
bb.0.entry:
|
||
|
|
liveins: $x10, $x11
|
||
|
|
|
||
|
|
; RV64I-LABEL: name: srl_i32
|
||
|
|
; RV64I: liveins: $x10, $x11
|
||
|
|
; RV64I-NEXT: {{ $}}
|
||
|
|
; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
|
||
|
|
; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
|
||
|
|
; RV64I-NEXT: [[SRLW:%[0-9]+]]:gpr = SRLW [[COPY]], [[COPY1]]
|
||
|
|
; RV64I-NEXT: $x10 = COPY [[SRLW]]
|
||
|
|
; RV64I-NEXT: PseudoRET implicit $x10
|
||
|
|
%0:gprb(s64) = COPY $x10
|
||
|
|
%1:gprb(s32) = G_TRUNC %0(s64)
|
||
|
|
%2:gprb(s64) = COPY $x11
|
||
|
|
%3:gprb(s32) = G_TRUNC %2(s64)
|
||
|
|
%4:gprb(s32) = G_LSHR %1, %3(s32)
|
||
|
|
%5:gprb(s64) = G_ANYEXT %4(s32)
|
||
|
|
$x10 = COPY %5(s64)
|
||
|
|
PseudoRET implicit $x10
|
||
|
|
|
||
|
|
...
|
||
|
|
---
|
||
|
|
name: srli_i32
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
tracksRegLiveness: true
|
||
|
|
body: |
|
||
|
|
bb.0.entry:
|
||
|
|
liveins: $x10
|
||
|
|
|
||
|
|
; RV64I-LABEL: name: srli_i32
|
||
|
|
; RV64I: liveins: $x10
|
||
|
|
; RV64I-NEXT: {{ $}}
|
||
|
|
; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
|
||
|
|
; RV64I-NEXT: [[SRLIW:%[0-9]+]]:gpr = SRLIW [[COPY]], 31
|
||
|
|
; RV64I-NEXT: $x10 = COPY [[SRLIW]]
|
||
|
|
; RV64I-NEXT: PseudoRET implicit $x10
|
||
|
|
%0:gprb(s64) = COPY $x10
|
||
|
|
%1:gprb(s32) = G_TRUNC %0(s64)
|
||
|
|
%2:gprb(s64) = G_CONSTANT i64 31
|
||
|
|
%3:gprb(s32) = G_LSHR %1, %2(s64)
|
||
|
|
%4:gprb(s64) = G_ANYEXT %3(s32)
|
||
|
|
$x10 = COPY %4(s64)
|
||
|
|
PseudoRET implicit $x10
|
||
|
|
|
||
|
|
...
|
||
|
|
---
|
||
|
|
name: add_i64
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
tracksRegLiveness: true
|
||
|
|
body: |
|
||
|
|
bb.0.entry:
|
||
|
|
liveins: $x10, $x11
|
||
|
|
|
||
|
|
; RV64I-LABEL: name: add_i64
|
||
|
|
; RV64I: liveins: $x10, $x11
|
||
|
|
; RV64I-NEXT: {{ $}}
|
||
|
|
; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
|
||
|
|
; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
|
||
|
|
; RV64I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY]], [[COPY1]]
|
||
|
|
; RV64I-NEXT: $x10 = COPY [[ADD]]
|
||
|
|
; RV64I-NEXT: PseudoRET implicit $x10
|
||
|
|
%0:gprb(s64) = COPY $x10
|
||
|
|
%1:gprb(s64) = COPY $x11
|
||
|
|
%2:gprb(s64) = G_ADD %0, %1
|
||
|
|
$x10 = COPY %2(s64)
|
||
|
|
PseudoRET implicit $x10
|
||
|
|
|
||
|
|
...
|
||
|
|
---
|
||
|
|
name: addi_i64
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
tracksRegLiveness: true
|
||
|
|
body: |
|
||
|
|
bb.0.entry:
|
||
|
|
liveins: $x10
|
||
|
|
|
||
|
|
; RV64I-LABEL: name: addi_i64
|
||
|
|
; RV64I: liveins: $x10
|
||
|
|
; RV64I-NEXT: {{ $}}
|
||
|
|
; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
|
||
|
|
; RV64I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY]], 1234
|
||
|
|
; RV64I-NEXT: $x10 = COPY [[ADDI]]
|
||
|
|
; RV64I-NEXT: PseudoRET implicit $x10
|
||
|
|
%0:gprb(s64) = COPY $x10
|
||
|
|
%1:gprb(s64) = G_CONSTANT i64 1234
|
||
|
|
%2:gprb(s64) = G_ADD %0, %1
|
||
|
|
$x10 = COPY %2(s64)
|
||
|
|
PseudoRET implicit $x10
|
||
|
|
|
||
|
|
...
|
||
|
|
---
|
||
|
|
name: sub_i64
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
tracksRegLiveness: true
|
||
|
|
body: |
|
||
|
|
bb.0.entry:
|
||
|
|
liveins: $x10, $x11
|
||
|
|
|
||
|
|
; RV64I-LABEL: name: sub_i64
|
||
|
|
; RV64I: liveins: $x10, $x11
|
||
|
|
; RV64I-NEXT: {{ $}}
|
||
|
|
; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
|
||
|
|
; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
|
||
|
|
; RV64I-NEXT: [[SUB:%[0-9]+]]:gpr = SUB [[COPY]], [[COPY1]]
|
||
|
|
; RV64I-NEXT: $x10 = COPY [[SUB]]
|
||
|
|
; RV64I-NEXT: PseudoRET implicit $x10
|
||
|
|
%0:gprb(s64) = COPY $x10
|
||
|
|
%1:gprb(s64) = COPY $x11
|
||
|
|
%2:gprb(s64) = G_SUB %0, %1
|
||
|
|
$x10 = COPY %2(s64)
|
||
|
|
PseudoRET implicit $x10
|
||
|
|
|
||
|
|
...
|
||
|
|
---
|
||
|
|
name: subi_i64
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
tracksRegLiveness: true
|
||
|
|
body: |
|
||
|
|
bb.0.entry:
|
||
|
|
liveins: $x10
|
||
|
|
|
||
|
|
; RV64I-LABEL: name: subi_i64
|
||
|
|
; RV64I: liveins: $x10
|
||
|
|
; RV64I-NEXT: {{ $}}
|
||
|
|
; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
|
||
|
|
; RV64I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY]], 1234
|
||
|
|
; RV64I-NEXT: $x10 = COPY [[ADDI]]
|
||
|
|
; RV64I-NEXT: PseudoRET implicit $x10
|
||
|
|
%0:gprb(s64) = COPY $x10
|
||
|
|
%1:gprb(s64) = G_CONSTANT i64 -1234
|
||
|
|
%2:gprb(s64) = G_SUB %0, %1
|
||
|
|
$x10 = COPY %2(s64)
|
||
|
|
PseudoRET implicit $x10
|
||
|
|
|
||
|
|
...
|
||
|
|
---
|
||
|
|
name: sll_i64
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
tracksRegLiveness: true
|
||
|
|
body: |
|
||
|
|
bb.0.entry:
|
||
|
|
liveins: $x10, $x11
|
||
|
|
|
||
|
|
; RV64I-LABEL: name: sll_i64
|
||
|
|
; RV64I: liveins: $x10, $x11
|
||
|
|
; RV64I-NEXT: {{ $}}
|
||
|
|
; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
|
||
|
|
; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
|
||
|
|
; RV64I-NEXT: [[SLL:%[0-9]+]]:gpr = SLL [[COPY]], [[COPY1]]
|
||
|
|
; RV64I-NEXT: $x10 = COPY [[SLL]]
|
||
|
|
; RV64I-NEXT: PseudoRET implicit $x10
|
||
|
|
%0:gprb(s64) = COPY $x10
|
||
|
|
%1:gprb(s64) = COPY $x11
|
||
|
|
%2:gprb(s64) = G_SHL %0, %1
|
||
|
|
$x10 = COPY %2(s64)
|
||
|
|
PseudoRET implicit $x10
|
||
|
|
|
||
|
|
...
|
||
|
|
---
|
||
|
|
name: slli_i64
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
tracksRegLiveness: true
|
||
|
|
body: |
|
||
|
|
bb.0.entry:
|
||
|
|
liveins: $x10
|
||
|
|
|
||
|
|
; RV64I-LABEL: name: slli_i64
|
||
|
|
; RV64I: liveins: $x10
|
||
|
|
; RV64I-NEXT: {{ $}}
|
||
|
|
; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
|
||
|
|
; RV64I-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[COPY]], 63
|
||
|
|
; RV64I-NEXT: $x10 = COPY [[SLLI]]
|
||
|
|
; RV64I-NEXT: PseudoRET implicit $x10
|
||
|
|
%0:gprb(s64) = COPY $x10
|
||
|
|
%1:gprb(s64) = G_CONSTANT i64 63
|
||
|
|
%2:gprb(s64) = G_SHL %0, %1
|
||
|
|
$x10 = COPY %2(s64)
|
||
|
|
PseudoRET implicit $x10
|
||
|
|
|
||
|
|
...
|
||
|
|
---
|
||
|
|
name: sra_i64
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
tracksRegLiveness: true
|
||
|
|
body: |
|
||
|
|
bb.0.entry:
|
||
|
|
liveins: $x10, $x11
|
||
|
|
|
||
|
|
; RV64I-LABEL: name: sra_i64
|
||
|
|
; RV64I: liveins: $x10, $x11
|
||
|
|
; RV64I-NEXT: {{ $}}
|
||
|
|
; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
|
||
|
|
; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
|
||
|
|
; RV64I-NEXT: [[SRA:%[0-9]+]]:gpr = SRA [[COPY]], [[COPY1]]
|
||
|
|
; RV64I-NEXT: $x10 = COPY [[SRA]]
|
||
|
|
; RV64I-NEXT: PseudoRET implicit $x10
|
||
|
|
%0:gprb(s64) = COPY $x10
|
||
|
|
%1:gprb(s64) = COPY $x11
|
||
|
|
%2:gprb(s64) = G_ASHR %0, %1
|
||
|
|
$x10 = COPY %2(s64)
|
||
|
|
PseudoRET implicit $x10
|
||
|
|
|
||
|
|
...
|
||
|
|
---
|
||
|
|
name: srai_i64
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
tracksRegLiveness: true
|
||
|
|
body: |
|
||
|
|
bb.0.entry:
|
||
|
|
liveins: $x10
|
||
|
|
|
||
|
|
; RV64I-LABEL: name: srai_i64
|
||
|
|
; RV64I: liveins: $x10
|
||
|
|
; RV64I-NEXT: {{ $}}
|
||
|
|
; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
|
||
|
|
; RV64I-NEXT: [[SRAI:%[0-9]+]]:gpr = SRAI [[COPY]], 63
|
||
|
|
; RV64I-NEXT: $x10 = COPY [[SRAI]]
|
||
|
|
; RV64I-NEXT: PseudoRET implicit $x10
|
||
|
|
%0:gprb(s64) = COPY $x10
|
||
|
|
%1:gprb(s64) = G_CONSTANT i64 63
|
||
|
|
%2:gprb(s64) = G_ASHR %0, %1
|
||
|
|
$x10 = COPY %2(s64)
|
||
|
|
PseudoRET implicit $x10
|
||
|
|
|
||
|
|
...
|
||
|
|
---
|
||
|
|
name: lshr_i64
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
tracksRegLiveness: true
|
||
|
|
body: |
|
||
|
|
bb.0.entry:
|
||
|
|
liveins: $x10, $x11
|
||
|
|
|
||
|
|
; RV64I-LABEL: name: lshr_i64
|
||
|
|
; RV64I: liveins: $x10, $x11
|
||
|
|
; RV64I-NEXT: {{ $}}
|
||
|
|
; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
|
||
|
|
; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
|
||
|
|
; RV64I-NEXT: [[SRL:%[0-9]+]]:gpr = SRL [[COPY]], [[COPY1]]
|
||
|
|
; RV64I-NEXT: $x10 = COPY [[SRL]]
|
||
|
|
; RV64I-NEXT: PseudoRET implicit $x10
|
||
|
|
%0:gprb(s64) = COPY $x10
|
||
|
|
%1:gprb(s64) = COPY $x11
|
||
|
|
%2:gprb(s64) = G_LSHR %0, %1
|
||
|
|
$x10 = COPY %2(s64)
|
||
|
|
PseudoRET implicit $x10
|
||
|
|
|
||
|
|
...
|
||
|
|
---
|
||
|
|
name: srli_i64
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
tracksRegLiveness: true
|
||
|
|
body: |
|
||
|
|
bb.0.entry:
|
||
|
|
liveins: $x10
|
||
|
|
|
||
|
|
; RV64I-LABEL: name: srli_i64
|
||
|
|
; RV64I: liveins: $x10
|
||
|
|
; RV64I-NEXT: {{ $}}
|
||
|
|
; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
|
||
|
|
; RV64I-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[COPY]], 63
|
||
|
|
; RV64I-NEXT: $x10 = COPY [[SRLI]]
|
||
|
|
; RV64I-NEXT: PseudoRET implicit $x10
|
||
|
|
%0:gprb(s64) = COPY $x10
|
||
|
|
%1:gprb(s64) = G_CONSTANT i64 63
|
||
|
|
%2:gprb(s64) = G_LSHR %0, %1
|
||
|
|
$x10 = COPY %2(s64)
|
||
|
|
PseudoRET implicit $x10
|
||
|
|
|
||
|
|
...
|
||
|
|
---
|
||
|
|
name: and_i64
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
tracksRegLiveness: true
|
||
|
|
body: |
|
||
|
|
bb.0.entry:
|
||
|
|
liveins: $x10, $x11
|
||
|
|
|
||
|
|
; RV64I-LABEL: name: and_i64
|
||
|
|
; RV64I: liveins: $x10, $x11
|
||
|
|
; RV64I-NEXT: {{ $}}
|
||
|
|
; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
|
||
|
|
; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
|
||
|
|
; RV64I-NEXT: [[AND:%[0-9]+]]:gpr = AND [[COPY]], [[COPY1]]
|
||
|
|
; RV64I-NEXT: $x10 = COPY [[AND]]
|
||
|
|
; RV64I-NEXT: PseudoRET implicit $x10
|
||
|
|
%0:gprb(s64) = COPY $x10
|
||
|
|
%1:gprb(s64) = COPY $x11
|
||
|
|
%2:gprb(s64) = G_AND %0, %1
|
||
|
|
$x10 = COPY %2(s64)
|
||
|
|
PseudoRET implicit $x10
|
||
|
|
|
||
|
|
...
|
||
|
|
---
|
||
|
|
name: andi_i64
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
tracksRegLiveness: true
|
||
|
|
body: |
|
||
|
|
bb.0.entry:
|
||
|
|
liveins: $x10
|
||
|
|
|
||
|
|
; RV64I-LABEL: name: andi_i64
|
||
|
|
; RV64I: liveins: $x10
|
||
|
|
; RV64I-NEXT: {{ $}}
|
||
|
|
; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
|
||
|
|
; RV64I-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY]], 1234
|
||
|
|
; RV64I-NEXT: $x10 = COPY [[ANDI]]
|
||
|
|
; RV64I-NEXT: PseudoRET implicit $x10
|
||
|
|
%0:gprb(s64) = COPY $x10
|
||
|
|
%1:gprb(s64) = G_CONSTANT i64 1234
|
||
|
|
%2:gprb(s64) = G_AND %0, %1
|
||
|
|
$x10 = COPY %2(s64)
|
||
|
|
PseudoRET implicit $x10
|
||
|
|
|
||
|
|
...
|
||
|
|
---
|
||
|
|
name: or_i64
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
tracksRegLiveness: true
|
||
|
|
body: |
|
||
|
|
bb.0.entry:
|
||
|
|
liveins: $x10, $x11
|
||
|
|
|
||
|
|
; RV64I-LABEL: name: or_i64
|
||
|
|
; RV64I: liveins: $x10, $x11
|
||
|
|
; RV64I-NEXT: {{ $}}
|
||
|
|
; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
|
||
|
|
; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
|
||
|
|
; RV64I-NEXT: [[OR:%[0-9]+]]:gpr = OR [[COPY]], [[COPY1]]
|
||
|
|
; RV64I-NEXT: $x10 = COPY [[OR]]
|
||
|
|
; RV64I-NEXT: PseudoRET implicit $x10
|
||
|
|
%0:gprb(s64) = COPY $x10
|
||
|
|
%1:gprb(s64) = COPY $x11
|
||
|
|
%2:gprb(s64) = G_OR %0, %1
|
||
|
|
$x10 = COPY %2(s64)
|
||
|
|
PseudoRET implicit $x10
|
||
|
|
|
||
|
|
...
|
||
|
|
---
|
||
|
|
name: ori_i64
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
tracksRegLiveness: true
|
||
|
|
body: |
|
||
|
|
bb.0.entry:
|
||
|
|
liveins: $x10
|
||
|
|
|
||
|
|
; RV64I-LABEL: name: ori_i64
|
||
|
|
; RV64I: liveins: $x10
|
||
|
|
; RV64I-NEXT: {{ $}}
|
||
|
|
; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
|
||
|
|
; RV64I-NEXT: [[ORI:%[0-9]+]]:gpr = ORI [[COPY]], 1234
|
||
|
|
; RV64I-NEXT: $x10 = COPY [[ORI]]
|
||
|
|
; RV64I-NEXT: PseudoRET implicit $x10
|
||
|
|
%0:gprb(s64) = COPY $x10
|
||
|
|
%1:gprb(s64) = G_CONSTANT i64 1234
|
||
|
|
%2:gprb(s64) = G_OR %0, %1
|
||
|
|
$x10 = COPY %2(s64)
|
||
|
|
PseudoRET implicit $x10
|
||
|
|
|
||
|
|
...
|
||
|
|
---
|
||
|
|
name: xor_i64
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
tracksRegLiveness: true
|
||
|
|
body: |
|
||
|
|
bb.0.entry:
|
||
|
|
liveins: $x10, $x11
|
||
|
|
|
||
|
|
; RV64I-LABEL: name: xor_i64
|
||
|
|
; RV64I: liveins: $x10, $x11
|
||
|
|
; RV64I-NEXT: {{ $}}
|
||
|
|
; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
|
||
|
|
; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
|
||
|
|
; RV64I-NEXT: [[XOR:%[0-9]+]]:gpr = XOR [[COPY]], [[COPY1]]
|
||
|
|
; RV64I-NEXT: $x10 = COPY [[XOR]]
|
||
|
|
; RV64I-NEXT: PseudoRET implicit $x10
|
||
|
|
%0:gprb(s64) = COPY $x10
|
||
|
|
%1:gprb(s64) = COPY $x11
|
||
|
|
%2:gprb(s64) = G_XOR %0, %1
|
||
|
|
$x10 = COPY %2(s64)
|
||
|
|
PseudoRET implicit $x10
|
||
|
|
|
||
|
|
...
|
||
|
|
---
|
||
|
|
name: xori_i64
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
tracksRegLiveness: true
|
||
|
|
body: |
|
||
|
|
bb.0.entry:
|
||
|
|
liveins: $x10
|
||
|
|
|
||
|
|
; RV64I-LABEL: name: xori_i64
|
||
|
|
; RV64I: liveins: $x10
|
||
|
|
; RV64I-NEXT: {{ $}}
|
||
|
|
; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
|
||
|
|
; RV64I-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[COPY]], 1234
|
||
|
|
; RV64I-NEXT: $x10 = COPY [[XORI]]
|
||
|
|
; RV64I-NEXT: PseudoRET implicit $x10
|
||
|
|
%0:gprb(s64) = COPY $x10
|
||
|
|
%1:gprb(s64) = G_CONSTANT i64 1234
|
||
|
|
%2:gprb(s64) = G_XOR %0, %1
|
||
|
|
$x10 = COPY %2(s64)
|
||
|
|
PseudoRET implicit $x10
|
||
|
|
|
||
|
|
...
|
||
|
|
---
|
||
|
|
name: add_i128
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
tracksRegLiveness: true
|
||
|
|
body: |
|
||
|
|
bb.0.entry:
|
||
|
|
liveins: $x10, $x11, $x12, $x13
|
||
|
|
|
||
|
|
; RV64I-LABEL: name: add_i128
|
||
|
|
; RV64I: liveins: $x10, $x11, $x12, $x13
|
||
|
|
; RV64I-NEXT: {{ $}}
|
||
|
|
; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
|
||
|
|
; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
|
||
|
|
; RV64I-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12
|
||
|
|
; RV64I-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x13
|
||
|
|
; RV64I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY]], [[COPY2]]
|
||
|
|
; RV64I-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[ADD]], [[COPY2]]
|
||
|
|
; RV64I-NEXT: [[ADD1:%[0-9]+]]:gpr = ADD [[COPY1]], [[COPY3]]
|
||
|
|
; RV64I-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[SLTU]], 1
|
||
|
|
; RV64I-NEXT: [[ADD2:%[0-9]+]]:gpr = ADD [[ADD1]], [[ANDI]]
|
||
|
|
; RV64I-NEXT: $x10 = COPY [[ADD]]
|
||
|
|
; RV64I-NEXT: $x11 = COPY [[ADD2]]
|
||
|
|
; RV64I-NEXT: PseudoRET implicit $x10, implicit $x11
|
||
|
|
%0:gprb(s64) = COPY $x10
|
||
|
|
%1:gprb(s64) = COPY $x11
|
||
|
|
%2:gprb(s64) = COPY $x12
|
||
|
|
%3:gprb(s64) = COPY $x13
|
||
|
|
%4:gprb(s64) = G_ADD %0, %2
|
||
|
|
%5:gprb(s64) = G_ICMP intpred(ult), %4(s64), %2
|
||
|
|
%6:gprb(s64) = G_ADD %1, %3
|
||
|
|
%7:gprb(s64) = G_CONSTANT i64 1
|
||
|
|
%8:gprb(s64) = G_AND %5, %7
|
||
|
|
%9:gprb(s64) = G_ADD %6, %8
|
||
|
|
$x10 = COPY %4(s64)
|
||
|
|
$x11 = COPY %9(s64)
|
||
|
|
PseudoRET implicit $x10, implicit $x11
|
||
|
|
|
||
|
|
...
|
||
|
|
---
|
||
|
|
name: sub_i128
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
tracksRegLiveness: true
|
||
|
|
body: |
|
||
|
|
bb.0.entry:
|
||
|
|
liveins: $x10, $x11, $x12, $x13
|
||
|
|
|
||
|
|
; RV64I-LABEL: name: sub_i128
|
||
|
|
; RV64I: liveins: $x10, $x11, $x12, $x13
|
||
|
|
; RV64I-NEXT: {{ $}}
|
||
|
|
; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
|
||
|
|
; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
|
||
|
|
; RV64I-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12
|
||
|
|
; RV64I-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x13
|
||
|
|
; RV64I-NEXT: [[SUB:%[0-9]+]]:gpr = SUB [[COPY]], [[COPY2]]
|
||
|
|
; RV64I-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[COPY]], [[COPY2]]
|
||
|
|
; RV64I-NEXT: [[SUB1:%[0-9]+]]:gpr = SUB [[COPY1]], [[COPY3]]
|
||
|
|
; RV64I-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[SLTU]], 1
|
||
|
|
; RV64I-NEXT: [[SUB2:%[0-9]+]]:gpr = SUB [[SUB1]], [[ANDI]]
|
||
|
|
; RV64I-NEXT: $x10 = COPY [[SUB]]
|
||
|
|
; RV64I-NEXT: $x11 = COPY [[SUB2]]
|
||
|
|
; RV64I-NEXT: PseudoRET implicit $x10, implicit $x11
|
||
|
|
%0:gprb(s64) = COPY $x10
|
||
|
|
%1:gprb(s64) = COPY $x11
|
||
|
|
%2:gprb(s64) = COPY $x12
|
||
|
|
%3:gprb(s64) = COPY $x13
|
||
|
|
%4:gprb(s64) = G_SUB %0, %2
|
||
|
|
%5:gprb(s64) = G_ICMP intpred(ult), %0(s64), %2
|
||
|
|
%6:gprb(s64) = G_SUB %1, %3
|
||
|
|
%7:gprb(s64) = G_CONSTANT i64 1
|
||
|
|
%8:gprb(s64) = G_AND %5, %7
|
||
|
|
%9:gprb(s64) = G_SUB %6, %8
|
||
|
|
$x10 = COPY %4(s64)
|
||
|
|
$x11 = COPY %9(s64)
|
||
|
|
PseudoRET implicit $x10, implicit $x11
|
||
|
|
|
||
|
|
...
|