107 lines
4 KiB
Text
107 lines
4 KiB
Text
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# RUN: llc -mtriple=riscv32 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
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# RUN: | FileCheck -check-prefixes=OUTLINED,RV32I-MO %s
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# RUN: llc -mtriple=riscv64 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
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# RUN: | FileCheck -check-prefixes=OUTLINED,RV64I-MO %s
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# CFIs are invisible (they can be outlined, but won't actually impact the outlining result) if there
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# is no need to unwind. CFIs will be stripped when we build outlined functions.
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--- |
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define void @func1(i32 %a, i32 %b) nounwind { ret void }
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define void @func2(i32 %a, i32 %b) nounwind { ret void }
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define void @func3(i32 %a, i32 %b) nounwind { ret void }
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...
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---
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name: func1
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x10, $x11
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; RV32I-MO-LABEL: name: func1
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; RV32I-MO: liveins: $x10, $x11
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; RV32I-MO-NEXT: {{ $}}
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; RV32I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
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; RV32I-MO-NEXT: PseudoRET
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; RV64I-MO-LABEL: name: func1
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; RV64I-MO: liveins: $x10, $x11
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; RV64I-MO-NEXT: {{ $}}
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; RV64I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
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; RV64I-MO-NEXT: PseudoRET
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$x10 = ORI $x10, 1023
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CFI_INSTRUCTION offset $x1, 0
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$x11 = ORI $x11, 1023
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CFI_INSTRUCTION offset $x1, -4
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$x12 = ADDI $x10, 17
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CFI_INSTRUCTION offset $x1, -8
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$x11 = AND $x12, $x11
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CFI_INSTRUCTION offset $x1, -12
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$x10 = SUB $x10, $x11
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PseudoRET
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...
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---
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name: func2
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x10, $x11
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; RV32I-MO-LABEL: name: func2
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; RV32I-MO: liveins: $x10, $x11
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; RV32I-MO-NEXT: {{ $}}
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; RV32I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
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; RV32I-MO-NEXT: PseudoRET
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; RV64I-MO-LABEL: name: func2
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; RV64I-MO: liveins: $x10, $x11
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; RV64I-MO-NEXT: {{ $}}
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; RV64I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
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; RV64I-MO-NEXT: PseudoRET
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$x10 = ORI $x10, 1023
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CFI_INSTRUCTION offset $x1, 0
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$x11 = ORI $x11, 1023
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CFI_INSTRUCTION offset $x1, -8
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$x12 = ADDI $x10, 17
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CFI_INSTRUCTION offset $x1, -4
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$x11 = AND $x12, $x11
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CFI_INSTRUCTION offset $x1, -12
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$x10 = SUB $x10, $x11
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PseudoRET
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...
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---
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name: func3
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x10, $x11
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; RV32I-MO-LABEL: name: func3
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; RV32I-MO: liveins: $x10, $x11
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; RV32I-MO-NEXT: {{ $}}
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; RV32I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
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; RV32I-MO-NEXT: PseudoRET
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; RV64I-MO-LABEL: name: func3
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; RV64I-MO: liveins: $x10, $x11
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; RV64I-MO-NEXT: {{ $}}
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; RV64I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
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; RV64I-MO-NEXT: PseudoRET
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$x10 = ORI $x10, 1023
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CFI_INSTRUCTION offset $x1, -12
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$x11 = ORI $x11, 1023
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CFI_INSTRUCTION offset $x1, -8
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$x12 = ADDI $x10, 17
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CFI_INSTRUCTION offset $x1, -4
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$x11 = AND $x12, $x11
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CFI_INSTRUCTION offset $x1, 0
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$x10 = SUB $x10, $x11
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PseudoRET
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# OUTLINED-LABEL: name: OUTLINED_FUNCTION_0
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# OUTLINED: liveins: $x11, $x10, $x5
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# OUTLINED-NEXT: {{ $}}
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# OUTLINED-NEXT: $x10 = ORI $x10, 1023
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# OUTLINED-NEXT: $x11 = ORI $x11, 1023
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# OUTLINED-NEXT: $x12 = ADDI $x10, 17
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# OUTLINED-NEXT: $x11 = AND $x12, $x11
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# OUTLINED-NEXT: $x10 = SUB $x10, $x11
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# OUTLINED-NEXT: $x0 = JALR $x5, 0
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