78 lines
2.4 KiB
LLVM
78 lines
2.4 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv64 -mattr=+zbb -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV64ZBB
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declare i32 @llvm.riscv.orc.b.i32(i32)
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define signext i32 @orcb32(i32 signext %a) nounwind {
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; RV64ZBB-LABEL: orcb32:
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; RV64ZBB: # %bb.0:
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; RV64ZBB-NEXT: orc.b a0, a0
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; RV64ZBB-NEXT: sext.w a0, a0
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; RV64ZBB-NEXT: ret
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%tmp = call i32 @llvm.riscv.orc.b.i32(i32 %a)
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ret i32 %tmp
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}
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define zeroext i32 @orcb32_zext(i32 zeroext %a) nounwind {
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; RV64ZBB-LABEL: orcb32_zext:
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; RV64ZBB: # %bb.0:
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; RV64ZBB-NEXT: orc.b a0, a0
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; RV64ZBB-NEXT: ret
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%tmp = call i32 @llvm.riscv.orc.b.i32(i32 %a)
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ret i32 %tmp
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}
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; Second and+or is redundant with the first, make sure we remove them.
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define signext i32 @orcb32_knownbits(i32 signext %a) nounwind {
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; RV64ZBB-LABEL: orcb32_knownbits:
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; RV64ZBB: # %bb.0:
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; RV64ZBB-NEXT: lui a1, 1044480
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; RV64ZBB-NEXT: and a0, a0, a1
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; RV64ZBB-NEXT: lui a1, 2048
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; RV64ZBB-NEXT: addi a1, a1, 1
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; RV64ZBB-NEXT: or a0, a0, a1
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; RV64ZBB-NEXT: orc.b a0, a0
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; RV64ZBB-NEXT: sext.w a0, a0
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; RV64ZBB-NEXT: ret
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%tmp = and i32 %a, 4278190080 ; 0xFF000000
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%tmp2 = or i32 %tmp, 8388609 ; 0x800001
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%tmp3 = call i32 @llvm.riscv.orc.b.i32(i32 %tmp2)
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%tmp4 = and i32 %tmp3, 4278190080 ; 0xFF000000
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%tmp5 = or i32 %tmp4, 16711935 ; 0xFF00FF
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ret i32 %tmp5
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}
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declare i64 @llvm.riscv.orc.b.i64(i64)
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define i64 @orcb64(i64 %a) nounwind {
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; RV64ZBB-LABEL: orcb64:
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; RV64ZBB: # %bb.0:
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; RV64ZBB-NEXT: orc.b a0, a0
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; RV64ZBB-NEXT: ret
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%tmp = call i64 @llvm.riscv.orc.b.i64(i64 %a)
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ret i64 %tmp
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}
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; Second and+or is redundant with the first, make sure we remove them.
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define i64 @orcb64_knownbits(i64 %a) nounwind {
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; RV64ZBB-LABEL: orcb64_knownbits:
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; RV64ZBB: # %bb.0:
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; RV64ZBB-NEXT: lui a1, 65535
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; RV64ZBB-NEXT: slli a1, a1, 12
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; RV64ZBB-NEXT: and a0, a0, a1
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; RV64ZBB-NEXT: lui a1, 256
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; RV64ZBB-NEXT: addiw a1, a1, 8
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; RV64ZBB-NEXT: slli a2, a1, 42
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; RV64ZBB-NEXT: add a1, a1, a2
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; RV64ZBB-NEXT: or a0, a0, a1
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; RV64ZBB-NEXT: orc.b a0, a0
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; RV64ZBB-NEXT: ret
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%tmp = and i64 %a, 1099494850560 ; 0x000000ffff000000
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%tmp2 = or i64 %tmp, 4611721202800525320 ; 0x4000200000100008
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%tmp3 = call i64 @llvm.riscv.orc.b.i64(i64 %tmp2)
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%tmp4 = and i64 %tmp3, 1099494850560 ; 0x000000ffff000000
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%tmp5 = or i64 %tmp4, 18374966855153418495 ; 0xff00ff0000ff00ff
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ret i64 %tmp5
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}
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