28 lines
1.1 KiB
ArmAsm
28 lines
1.1 KiB
ArmAsm
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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
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// --------------------------------------------------------------------------//
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// Invalid vector list
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sqcvt z0.h, {z0.s-z2.s}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: sqcvt z0.h, {z0.s-z2.s}
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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sqcvt z0.b, {z1.s-z4.s}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element type
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// CHECK-NEXT: sqcvt z0.b, {z1.s-z4.s}
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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sqcvt z0.h, {z1.d-z2.d}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: sqcvt z0.h, {z1.d-z2.d}
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid Register Suffix
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sqcvt z0.s, {z0.s-z1.s}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: sqcvt z0.s, {z0.s-z1.s}
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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