341 lines
10 KiB
ArmAsm
341 lines
10 KiB
ArmAsm
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
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// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
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// RUN: | llvm-objdump --no-print-imm-hex -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
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// RUN: | llvm-objdump --no-print-imm-hex -d --mattr=-sve - | FileCheck %s --check-prefix=CHECK-UNKNOWN
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// ---------------------------------------------------------------------------//
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// Test 64-bit form (x0) and its aliases
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// ---------------------------------------------------------------------------//
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uqinch x0
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// CHECK-INST: uqinch x0
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// CHECK-ENCODING: [0xe0,0xf7,0x70,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 0470f7e0 <unknown>
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uqinch x0, all
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// CHECK-INST: uqinch x0
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// CHECK-ENCODING: [0xe0,0xf7,0x70,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 0470f7e0 <unknown>
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uqinch x0, all, mul #1
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// CHECK-INST: uqinch x0
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// CHECK-ENCODING: [0xe0,0xf7,0x70,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 0470f7e0 <unknown>
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uqinch x0, all, mul #16
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// CHECK-INST: uqinch x0, all, mul #16
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// CHECK-ENCODING: [0xe0,0xf7,0x7f,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 047ff7e0 <unknown>
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// ---------------------------------------------------------------------------//
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// Test 32-bit form (w0) and its aliases
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// ---------------------------------------------------------------------------//
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uqinch w0
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// CHECK-INST: uqinch w0
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// CHECK-ENCODING: [0xe0,0xf7,0x60,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 0460f7e0 <unknown>
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uqinch w0, all
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// CHECK-INST: uqinch w0
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// CHECK-ENCODING: [0xe0,0xf7,0x60,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 0460f7e0 <unknown>
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uqinch w0, all, mul #1
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// CHECK-INST: uqinch w0
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// CHECK-ENCODING: [0xe0,0xf7,0x60,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 0460f7e0 <unknown>
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uqinch w0, all, mul #16
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// CHECK-INST: uqinch w0, all, mul #16
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// CHECK-ENCODING: [0xe0,0xf7,0x6f,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 046ff7e0 <unknown>
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uqinch w0, pow2
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// CHECK-INST: uqinch w0, pow2
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// CHECK-ENCODING: [0x00,0xf4,0x60,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 0460f400 <unknown>
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uqinch w0, pow2, mul #16
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// CHECK-INST: uqinch w0, pow2, mul #16
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// CHECK-ENCODING: [0x00,0xf4,0x6f,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 046ff400 <unknown>
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// ---------------------------------------------------------------------------//
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// Test vector form and aliases.
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// ---------------------------------------------------------------------------//
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uqinch z0.h
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// CHECK-INST: uqinch z0.h
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// CHECK-ENCODING: [0xe0,0xc7,0x60,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 0460c7e0 <unknown>
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uqinch z0.h, all
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// CHECK-INST: uqinch z0.h
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// CHECK-ENCODING: [0xe0,0xc7,0x60,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 0460c7e0 <unknown>
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uqinch z0.h, all, mul #1
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// CHECK-INST: uqinch z0.h
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// CHECK-ENCODING: [0xe0,0xc7,0x60,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 0460c7e0 <unknown>
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uqinch z0.h, all, mul #16
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// CHECK-INST: uqinch z0.h, all, mul #16
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// CHECK-ENCODING: [0xe0,0xc7,0x6f,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 046fc7e0 <unknown>
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uqinch z0.h, pow2
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// CHECK-INST: uqinch z0.h, pow2
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// CHECK-ENCODING: [0x00,0xc4,0x60,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 0460c400 <unknown>
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uqinch z0.h, pow2, mul #16
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// CHECK-INST: uqinch z0.h, pow2, mul #16
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// CHECK-ENCODING: [0x00,0xc4,0x6f,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 046fc400 <unknown>
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// ---------------------------------------------------------------------------//
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// Test all patterns for 64-bit form
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// ---------------------------------------------------------------------------//
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uqinch x0, pow2
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// CHECK-INST: uqinch x0, pow2
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// CHECK-ENCODING: [0x00,0xf4,0x70,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 0470f400 <unknown>
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uqinch x0, vl1
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// CHECK-INST: uqinch x0, vl1
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// CHECK-ENCODING: [0x20,0xf4,0x70,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 0470f420 <unknown>
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uqinch x0, vl2
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// CHECK-INST: uqinch x0, vl2
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// CHECK-ENCODING: [0x40,0xf4,0x70,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 0470f440 <unknown>
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uqinch x0, vl3
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// CHECK-INST: uqinch x0, vl3
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// CHECK-ENCODING: [0x60,0xf4,0x70,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 0470f460 <unknown>
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uqinch x0, vl4
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// CHECK-INST: uqinch x0, vl4
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// CHECK-ENCODING: [0x80,0xf4,0x70,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 0470f480 <unknown>
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uqinch x0, vl5
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// CHECK-INST: uqinch x0, vl5
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// CHECK-ENCODING: [0xa0,0xf4,0x70,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 0470f4a0 <unknown>
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uqinch x0, vl6
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// CHECK-INST: uqinch x0, vl6
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// CHECK-ENCODING: [0xc0,0xf4,0x70,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 0470f4c0 <unknown>
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uqinch x0, vl7
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// CHECK-INST: uqinch x0, vl7
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// CHECK-ENCODING: [0xe0,0xf4,0x70,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 0470f4e0 <unknown>
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uqinch x0, vl8
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// CHECK-INST: uqinch x0, vl8
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// CHECK-ENCODING: [0x00,0xf5,0x70,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 0470f500 <unknown>
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uqinch x0, vl16
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// CHECK-INST: uqinch x0, vl16
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// CHECK-ENCODING: [0x20,0xf5,0x70,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 0470f520 <unknown>
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uqinch x0, vl32
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// CHECK-INST: uqinch x0, vl32
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// CHECK-ENCODING: [0x40,0xf5,0x70,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 0470f540 <unknown>
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uqinch x0, vl64
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// CHECK-INST: uqinch x0, vl64
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// CHECK-ENCODING: [0x60,0xf5,0x70,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 0470f560 <unknown>
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uqinch x0, vl128
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// CHECK-INST: uqinch x0, vl128
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// CHECK-ENCODING: [0x80,0xf5,0x70,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 0470f580 <unknown>
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uqinch x0, vl256
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// CHECK-INST: uqinch x0, vl256
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// CHECK-ENCODING: [0xa0,0xf5,0x70,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 0470f5a0 <unknown>
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uqinch x0, #14
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// CHECK-INST: uqinch x0, #14
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// CHECK-ENCODING: [0xc0,0xf5,0x70,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 0470f5c0 <unknown>
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uqinch x0, #15
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// CHECK-INST: uqinch x0, #15
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// CHECK-ENCODING: [0xe0,0xf5,0x70,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 0470f5e0 <unknown>
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uqinch x0, #16
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// CHECK-INST: uqinch x0, #16
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// CHECK-ENCODING: [0x00,0xf6,0x70,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 0470f600 <unknown>
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uqinch x0, #17
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// CHECK-INST: uqinch x0, #17
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// CHECK-ENCODING: [0x20,0xf6,0x70,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 0470f620 <unknown>
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uqinch x0, #18
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// CHECK-INST: uqinch x0, #18
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// CHECK-ENCODING: [0x40,0xf6,0x70,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 0470f640 <unknown>
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uqinch x0, #19
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// CHECK-INST: uqinch x0, #19
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// CHECK-ENCODING: [0x60,0xf6,0x70,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 0470f660 <unknown>
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uqinch x0, #20
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// CHECK-INST: uqinch x0, #20
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// CHECK-ENCODING: [0x80,0xf6,0x70,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 0470f680 <unknown>
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uqinch x0, #21
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// CHECK-INST: uqinch x0, #21
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// CHECK-ENCODING: [0xa0,0xf6,0x70,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 0470f6a0 <unknown>
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uqinch x0, #22
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// CHECK-INST: uqinch x0, #22
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// CHECK-ENCODING: [0xc0,0xf6,0x70,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 0470f6c0 <unknown>
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uqinch x0, #23
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// CHECK-INST: uqinch x0, #23
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// CHECK-ENCODING: [0xe0,0xf6,0x70,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 0470f6e0 <unknown>
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uqinch x0, #24
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// CHECK-INST: uqinch x0, #24
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// CHECK-ENCODING: [0x00,0xf7,0x70,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 0470f700 <unknown>
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uqinch x0, #25
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// CHECK-INST: uqinch x0, #25
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// CHECK-ENCODING: [0x20,0xf7,0x70,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 0470f720 <unknown>
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uqinch x0, #26
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// CHECK-INST: uqinch x0, #26
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// CHECK-ENCODING: [0x40,0xf7,0x70,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 0470f740 <unknown>
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uqinch x0, #27
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// CHECK-INST: uqinch x0, #27
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// CHECK-ENCODING: [0x60,0xf7,0x70,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 0470f760 <unknown>
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uqinch x0, #28
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// CHECK-INST: uqinch x0, #28
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// CHECK-ENCODING: [0x80,0xf7,0x70,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 0470f780 <unknown>
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// --------------------------------------------------------------------------//
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// Test compatibility with MOVPRFX instruction.
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movprfx z0, z7
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// CHECK-INST: movprfx z0, z7
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// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 0420bce0 <unknown>
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uqinch z0.h
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// CHECK-INST: uqinch z0.h
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// CHECK-ENCODING: [0xe0,0xc7,0x60,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 0460c7e0 <unknown>
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movprfx z0, z7
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// CHECK-INST: movprfx z0, z7
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// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 0420bce0 <unknown>
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||
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uqinch z0.h, pow2, mul #16
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||
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// CHECK-INST: uqinch z0.h, pow2, mul #16
|
||
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// CHECK-ENCODING: [0x00,0xc4,0x6f,0x04]
|
||
|
|
// CHECK-ERROR: instruction requires: sve or sme
|
||
|
|
// CHECK-UNKNOWN: 046fc400 <unknown>
|
||
|
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|
||
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movprfx z0, z7
|
||
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|
// CHECK-INST: movprfx z0, z7
|
||
|
|
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
|
||
|
|
// CHECK-ERROR: instruction requires: sve or sme
|
||
|
|
// CHECK-UNKNOWN: 0420bce0 <unknown>
|
||
|
|
|
||
|
|
uqinch z0.h, pow2
|
||
|
|
// CHECK-INST: uqinch z0.h, pow2
|
||
|
|
// CHECK-ENCODING: [0x00,0xc4,0x60,0x04]
|
||
|
|
// CHECK-ERROR: instruction requires: sve or sme
|
||
|
|
// CHECK-UNKNOWN: 0460c400 <unknown>
|