244 lines
12 KiB
Text
244 lines
12 KiB
Text
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mattr=+m -mtriple=riscv32 -run-pass=legalizer %s -o - \
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# RUN: | FileCheck %s --check-prefix=RV32I
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# RUN: llc -mattr=+m -mtriple=riscv32 -mattr=+zbb -run-pass=legalizer %s -o - \
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# RUN: | FileCheck %s --check-prefix=RV32ZBB
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---
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name: ctpop_i8
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body: |
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bb.1:
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liveins: $x10
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; RV32I-LABEL: name: ctpop_i8
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; RV32I: liveins: $x10
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; RV32I-NEXT: {{ $}}
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; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
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; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
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; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
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; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
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; RV32I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C]](s32)
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; RV32I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 85
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; RV32I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
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; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[AND1]]
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; RV32I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
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; RV32I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
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; RV32I-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C4]]
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; RV32I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C3]](s32)
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; RV32I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 51
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; RV32I-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C5]]
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; RV32I-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C5]]
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; RV32I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND3]], [[AND4]]
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; RV32I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
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; RV32I-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[ADD]], [[C6]](s32)
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; RV32I-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LSHR2]], [[ADD]]
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; RV32I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
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; RV32I-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C7]]
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; RV32I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
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; RV32I-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND5]], [[C8]]
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; RV32I-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; RV32I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[MUL]], [[C9]](s32)
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; RV32I-NEXT: $x10 = COPY [[LSHR3]](s32)
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; RV32I-NEXT: PseudoRET implicit $x10
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;
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; RV32ZBB-LABEL: name: ctpop_i8
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; RV32ZBB: liveins: $x10
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; RV32ZBB-NEXT: {{ $}}
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; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
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; RV32ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
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; RV32ZBB-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
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; RV32ZBB-NEXT: [[CTPOP:%[0-9]+]]:_(s32) = G_CTPOP [[AND]](s32)
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; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTPOP]](s32)
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; RV32ZBB-NEXT: $x10 = COPY [[COPY1]](s32)
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; RV32ZBB-NEXT: PseudoRET implicit $x10
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%1:_(s32) = COPY $x10
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%0:_(s8) = G_TRUNC %1(s32)
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%2:_(s8) = G_CTPOP %0(s8)
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%3:_(s32) = G_ANYEXT %2(s8)
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$x10 = COPY %3(s32)
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PseudoRET implicit $x10
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...
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---
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name: ctpop_i16
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body: |
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bb.1:
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liveins: $x10
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; RV32I-LABEL: name: ctpop_i16
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; RV32I: liveins: $x10
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; RV32I-NEXT: {{ $}}
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; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
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; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
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; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
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; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
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; RV32I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C]](s32)
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; RV32I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 21845
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; RV32I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
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; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[AND1]]
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; RV32I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
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; RV32I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
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; RV32I-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C4]]
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; RV32I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C3]](s32)
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; RV32I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 13107
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; RV32I-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C5]]
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; RV32I-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C5]]
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; RV32I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND3]], [[AND4]]
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; RV32I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
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; RV32I-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[ADD]], [[C6]](s32)
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; RV32I-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LSHR2]], [[ADD]]
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; RV32I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 3855
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; RV32I-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C7]]
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; RV32I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 257
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; RV32I-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND5]], [[C8]]
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; RV32I-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
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; RV32I-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
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; RV32I-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C10]]
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; RV32I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[C9]](s32)
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; RV32I-NEXT: $x10 = COPY [[LSHR3]](s32)
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; RV32I-NEXT: PseudoRET implicit $x10
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;
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; RV32ZBB-LABEL: name: ctpop_i16
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; RV32ZBB: liveins: $x10
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; RV32ZBB-NEXT: {{ $}}
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; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
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; RV32ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
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; RV32ZBB-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
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; RV32ZBB-NEXT: [[CTPOP:%[0-9]+]]:_(s32) = G_CTPOP [[AND]](s32)
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; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTPOP]](s32)
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; RV32ZBB-NEXT: $x10 = COPY [[COPY1]](s32)
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; RV32ZBB-NEXT: PseudoRET implicit $x10
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%1:_(s32) = COPY $x10
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%0:_(s16) = G_TRUNC %1(s32)
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%2:_(s16) = G_CTPOP %0(s16)
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%3:_(s32) = G_ANYEXT %2(s16)
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$x10 = COPY %3(s32)
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PseudoRET implicit $x10
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...
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---
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name: ctpop_i32
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body: |
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bb.1:
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liveins: $x10
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; RV32I-LABEL: name: ctpop_i32
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; RV32I: liveins: $x10
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; RV32I-NEXT: {{ $}}
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; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
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; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
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; RV32I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
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; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1431655765
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; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
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; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[AND]]
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; RV32I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
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; RV32I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[SUB]], [[C2]](s32)
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; RV32I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 858993459
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; RV32I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
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; RV32I-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C3]]
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; RV32I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND1]], [[AND2]]
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; RV32I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
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; RV32I-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[ADD]], [[C4]](s32)
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; RV32I-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LSHR2]], [[ADD]]
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; RV32I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 252645135
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; RV32I-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C5]]
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; RV32I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 16843009
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; RV32I-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND3]], [[C6]]
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; RV32I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
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; RV32I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[MUL]], [[C7]](s32)
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; RV32I-NEXT: $x10 = COPY [[LSHR3]](s32)
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; RV32I-NEXT: PseudoRET implicit $x10
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;
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; RV32ZBB-LABEL: name: ctpop_i32
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; RV32ZBB: liveins: $x10
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; RV32ZBB-NEXT: {{ $}}
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; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
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; RV32ZBB-NEXT: [[CTPOP:%[0-9]+]]:_(s32) = G_CTPOP [[COPY]](s32)
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; RV32ZBB-NEXT: $x10 = COPY [[CTPOP]](s32)
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; RV32ZBB-NEXT: PseudoRET implicit $x10
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%0:_(s32) = COPY $x10
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%1:_(s32) = G_CTPOP %0(s32)
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$x10 = COPY %1(s32)
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PseudoRET implicit $x10
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...
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---
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name: ctpop_i64
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body: |
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bb.1:
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liveins: $x10, $x11
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; RV32I-LABEL: name: ctpop_i64
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; RV32I: liveins: $x10, $x11
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; RV32I-NEXT: {{ $}}
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; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
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; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
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; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
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; RV32I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
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; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1431655765
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; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
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; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[AND]]
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; RV32I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
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; RV32I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[SUB]], [[C2]](s32)
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; RV32I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 858993459
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; RV32I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
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; RV32I-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C3]]
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; RV32I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND1]], [[AND2]]
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; RV32I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
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; RV32I-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[ADD]], [[C4]](s32)
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; RV32I-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LSHR2]], [[ADD]]
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; RV32I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 252645135
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; RV32I-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C5]]
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; RV32I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 16843009
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; RV32I-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND3]], [[C6]]
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; RV32I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
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; RV32I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[MUL]], [[C7]](s32)
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; RV32I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
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; RV32I-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C8]](s32)
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; RV32I-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 1431655765
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; RV32I-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C9]]
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; RV32I-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[AND4]]
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; RV32I-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
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; RV32I-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[SUB1]], [[C10]](s32)
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; RV32I-NEXT: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 858993459
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; RV32I-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C11]]
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; RV32I-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[SUB1]], [[C11]]
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; RV32I-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[AND5]], [[AND6]]
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; RV32I-NEXT: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
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; RV32I-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[ADD2]], [[C12]](s32)
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; RV32I-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[LSHR6]], [[ADD2]]
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; RV32I-NEXT: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 252645135
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; RV32I-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[ADD3]], [[C13]]
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; RV32I-NEXT: [[C14:%[0-9]+]]:_(s32) = G_CONSTANT i32 16843009
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; RV32I-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[AND7]], [[C14]]
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; RV32I-NEXT: [[C15:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
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; RV32I-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[MUL1]], [[C15]](s32)
|
||
|
|
; RV32I-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[LSHR7]], [[LSHR3]]
|
||
|
|
; RV32I-NEXT: [[C16:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
|
||
|
|
; RV32I-NEXT: $x10 = COPY [[ADD4]](s32)
|
||
|
|
; RV32I-NEXT: $x11 = COPY [[C16]](s32)
|
||
|
|
; RV32I-NEXT: PseudoRET implicit $x10, implicit $x11
|
||
|
|
;
|
||
|
|
; RV32ZBB-LABEL: name: ctpop_i64
|
||
|
|
; RV32ZBB: liveins: $x10, $x11
|
||
|
|
; RV32ZBB-NEXT: {{ $}}
|
||
|
|
; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
|
||
|
|
; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
|
||
|
|
; RV32ZBB-NEXT: [[CTPOP:%[0-9]+]]:_(s32) = G_CTPOP [[COPY]](s32)
|
||
|
|
; RV32ZBB-NEXT: [[CTPOP1:%[0-9]+]]:_(s32) = G_CTPOP [[COPY1]](s32)
|
||
|
|
; RV32ZBB-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[CTPOP1]], [[CTPOP]]
|
||
|
|
; RV32ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
|
||
|
|
; RV32ZBB-NEXT: $x10 = COPY [[ADD]](s32)
|
||
|
|
; RV32ZBB-NEXT: $x11 = COPY [[C]](s32)
|
||
|
|
; RV32ZBB-NEXT: PseudoRET implicit $x10, implicit $x11
|
||
|
|
%1:_(s32) = COPY $x10
|
||
|
|
%2:_(s32) = COPY $x11
|
||
|
|
%0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)
|
||
|
|
%3:_(s64) = G_CTPOP %0(s64)
|
||
|
|
%4:_(s32), %5:_(s32) = G_UNMERGE_VALUES %3(s64)
|
||
|
|
$x10 = COPY %4(s32)
|
||
|
|
$x11 = COPY %5(s32)
|
||
|
|
PseudoRET implicit $x10, implicit $x11
|
||
|
|
|
||
|
|
...
|