bolt/deps/llvm-18.1.8/llvm/test/CodeGen/X86/GlobalISel/legalize-and-v128.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+sse2 -run-pass=legalizer %s -o - | FileCheck %s
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx  -run-pass=legalizer %s -o - | FileCheck %s
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx2 -run-pass=legalizer %s -o - | FileCheck %s

--- |
  define void @test_and_v16i8() {
    %ret = and <16 x i8> undef, undef
    ret void
  }

  define void @test_and_v8i16() {
    %ret = and <8 x i16> undef, undef
    ret void
  }

  define void @test_and_v4i32() {
    %ret = and <4 x i32> undef, undef
    ret void
  }

  define void @test_and_v2i64() {
    %ret = and <2 x i64> undef, undef
    ret void
  }
...
---
name:            test_and_v16i8
alignment:       16
legalized:       false
regBankSelected: false
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
body:             |
  bb.1 (%ir-block.0):
    liveins: $xmm0, $xmm1

    ; CHECK-LABEL: name: test_and_v16i8
    ; CHECK: liveins: $xmm0, $xmm1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
    ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<16 x s8>) = G_AND [[DEF]], [[DEF1]]
    ; CHECK-NEXT: $xmm0 = COPY [[AND]](<16 x s8>)
    ; CHECK-NEXT: RET 0
    %0(<16 x s8>) = IMPLICIT_DEF
    %1(<16 x s8>) = IMPLICIT_DEF
    %2(<16 x s8>) = G_AND %0, %1
    $xmm0 = COPY %2
    RET 0
...
---
name:            test_and_v8i16
alignment:       16
legalized:       false
regBankSelected: false
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
body:             |
  bb.1 (%ir-block.0):
    liveins: $xmm0, $xmm1

    ; CHECK-LABEL: name: test_and_v8i16
    ; CHECK: liveins: $xmm0, $xmm1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
    ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<8 x s16>) = G_AND [[DEF]], [[DEF1]]
    ; CHECK-NEXT: $xmm0 = COPY [[AND]](<8 x s16>)
    ; CHECK-NEXT: RET 0
    %0(<8 x s16>) = IMPLICIT_DEF
    %1(<8 x s16>) = IMPLICIT_DEF
    %2(<8 x s16>) = G_AND %0, %1
    $xmm0 = COPY %2
    RET 0
...
---
name:            test_and_v4i32
alignment:       16
legalized:       false
regBankSelected: false
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
body:             |
  bb.1 (%ir-block.0):
    liveins: $xmm0, $xmm1

    ; CHECK-LABEL: name: test_and_v4i32
    ; CHECK: liveins: $xmm0, $xmm1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
    ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<4 x s32>) = G_AND [[DEF]], [[DEF1]]
    ; CHECK-NEXT: $xmm0 = COPY [[AND]](<4 x s32>)
    ; CHECK-NEXT: RET 0
    %0(<4 x s32>) = IMPLICIT_DEF
    %1(<4 x s32>) = IMPLICIT_DEF
    %2(<4 x s32>) = G_AND %0, %1
    $xmm0 = COPY %2
    RET 0
...
---
name:            test_and_v2i64
alignment:       16
legalized:       false
regBankSelected: false
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
body:             |
  bb.1 (%ir-block.0):
    liveins: $xmm0, $xmm1

    ; CHECK-LABEL: name: test_and_v2i64
    ; CHECK: liveins: $xmm0, $xmm1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
    ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[DEF1]]
    ; CHECK-NEXT: $xmm0 = COPY [[AND]](<2 x s64>)
    ; CHECK-NEXT: RET 0
    %0(<2 x s64>) = IMPLICIT_DEF
    %1(<2 x s64>) = IMPLICIT_DEF
    %2(<2 x s64>) = G_AND %0, %1
    $xmm0 = COPY %2
    RET 0
...