192 lines
6.2 KiB
Text
192 lines
6.2 KiB
Text
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs -o - %s | FileCheck %s
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# Post-legalizer should not generate illegal extending loads
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---
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name: zextload_from_inreg
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tracksRegLiveness: true
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legalized: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; CHECK-LABEL: name: zextload_from_inreg
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; CHECK: liveins: $vgpr0_vgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
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; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p1) :: (load (s64), addrspace 1)
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; CHECK-NEXT: %k:_(s64) = G_CONSTANT i64 4294967295
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; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[LOAD]], %k
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; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[AND]](s64)
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%0:_(p1) = COPY $vgpr0_vgpr1
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%1:_(s64) = G_LOAD %0 :: (load (s64), align 8, addrspace 1)
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%k:_(s64) = G_CONSTANT i64 4294967295
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%2:_(s64) = G_AND %1, %k
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$vgpr0_vgpr1 = COPY %2
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...
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# Legal to fold into zextload
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---
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name: zext_inreg_8_zextload_s32
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tracksRegLiveness: true
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legalized: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; CHECK-LABEL: name: zext_inreg_8_zextload_s32
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; CHECK: liveins: $vgpr0_vgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
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; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (load (s8), align 4, addrspace 1)
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; CHECK-NEXT: $vgpr0 = COPY [[ZEXTLOAD]](s32)
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%0:_(p1) = COPY $vgpr0_vgpr1
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%1:_(s32) = G_LOAD %0 :: (load (s32), align 4, addrspace 1)
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%k:_(s32) = G_CONSTANT i32 255
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%2:_(s32) = G_AND %1, %k
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$vgpr0 = COPY %2
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...
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---
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name: zext_inreg_7_zextload_s32
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tracksRegLiveness: true
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legalized: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; CHECK-LABEL: name: zext_inreg_7_zextload_s32
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; CHECK: liveins: $vgpr0_vgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
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; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), addrspace 1)
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; CHECK-NEXT: %k:_(s32) = G_CONSTANT i32 127
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; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], %k
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; CHECK-NEXT: $vgpr0 = COPY [[AND]](s32)
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%0:_(p1) = COPY $vgpr0_vgpr1
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%1:_(s32) = G_LOAD %0 :: (load (s32), align 4, addrspace 1)
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%k:_(s32) = G_CONSTANT i32 127
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%2:_(s32) = G_AND %1, %k
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$vgpr0 = COPY %2
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...
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---
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name: zext_inreg_9_zextload_s32
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tracksRegLiveness: true
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legalized: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; CHECK-LABEL: name: zext_inreg_9_zextload_s32
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; CHECK: liveins: $vgpr0_vgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
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; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), addrspace 1)
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; CHECK-NEXT: %k:_(s32) = G_CONSTANT i32 511
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; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], %k
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; CHECK-NEXT: $vgpr0 = COPY [[AND]](s32)
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%0:_(p1) = COPY $vgpr0_vgpr1
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%1:_(s32) = G_LOAD %0 :: (load (s32), align 4, addrspace 1)
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%k:_(s32) = G_CONSTANT i32 511
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%2:_(s32) = G_AND %1, %k
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$vgpr0 = COPY %2
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...
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# Legal to fold into zextload
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---
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name: zext_inreg_16_zextload_s32
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tracksRegLiveness: true
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legalized: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; CHECK-LABEL: name: zext_inreg_16_zextload_s32
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; CHECK: liveins: $vgpr0_vgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
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; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (load (s16), align 4, addrspace 1)
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; CHECK-NEXT: $vgpr0 = COPY [[ZEXTLOAD]](s32)
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%0:_(p1) = COPY $vgpr0_vgpr1
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%1:_(s32) = G_LOAD %0 :: (load (s32), align 4, addrspace 1)
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%k:_(s32) = G_CONSTANT i32 65535
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%2:_(s32) = G_AND %1, %k
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$vgpr0 = COPY %2
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...
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---
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name: zext_inreg_8_zextload_s8
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tracksRegLiveness: true
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legalized: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; CHECK-LABEL: name: zext_inreg_8_zextload_s8
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; CHECK: liveins: $vgpr0_vgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
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; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (load (s8), addrspace 1)
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; CHECK-NEXT: $vgpr0 = COPY [[ZEXTLOAD]](s32)
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%0:_(p1) = COPY $vgpr0_vgpr1
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%1:_(s32) = G_LOAD %0 :: (load (s8), align 1, addrspace 1)
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%k:_(s32) = G_CONSTANT i32 255
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%2:_(s32) = G_AND %1, %k
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$vgpr0 = COPY %2
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...
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---
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name: zext_inreg_8_zextload_s8_volatile
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tracksRegLiveness: true
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legalized: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; CHECK-LABEL: name: zext_inreg_8_zextload_s8_volatile
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; CHECK: liveins: $vgpr0_vgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
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; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (volatile load (s8), addrspace 1)
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; CHECK-NEXT: $vgpr0 = COPY [[ZEXTLOAD]](s32)
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%0:_(p1) = COPY $vgpr0_vgpr1
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%1:_(s32) = G_LOAD %0 :: (volatile load (s8), align 1, addrspace 1)
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%k:_(s32) = G_CONSTANT i32 255
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%2:_(s32) = G_AND %1, %k
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$vgpr0 = COPY %2
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...
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---
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name: zext_inreg_16_zextload_s16
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tracksRegLiveness: true
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legalized: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; CHECK-LABEL: name: zext_inreg_16_zextload_s16
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; CHECK: liveins: $vgpr0_vgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
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; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (load (s16), addrspace 1)
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; CHECK-NEXT: $vgpr0 = COPY [[ZEXTLOAD]](s32)
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%0:_(p1) = COPY $vgpr0_vgpr1
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%1:_(s32) = G_LOAD %0 :: (load (s16), align 2, addrspace 1)
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%k:_(s32) = G_CONSTANT i32 65535
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%2:_(s32) = G_AND %1, %k
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$vgpr0 = COPY %2
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...
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---
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name: zext_inreg_16_zextload_s16_volatile
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tracksRegLiveness: true
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legalized: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; CHECK-LABEL: name: zext_inreg_16_zextload_s16_volatile
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; CHECK: liveins: $vgpr0_vgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
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; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (volatile load (s16), addrspace 1)
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; CHECK-NEXT: $vgpr0 = COPY [[ZEXTLOAD]](s32)
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%0:_(p1) = COPY $vgpr0_vgpr1
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%1:_(s32) = G_LOAD %0 :: (volatile load (s16), align 2, addrspace 1)
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%k:_(s32) = G_CONSTANT i32 65535
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%2:_(s32) = G_AND %1, %k
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$vgpr0 = COPY %2
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...
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