64 lines
2.3 KiB
TableGen
64 lines
2.3 KiB
TableGen
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//===- Xtensa.td - Describe the Xtensa Target Machine ------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Target-independent interfaces
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//===----------------------------------------------------------------------===//
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include "llvm/Target/Target.td"
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//===----------------------------------------------------------------------===//
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// Subtarget Features.
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//===----------------------------------------------------------------------===//
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def FeatureDensity : SubtargetFeature<"density", "HasDensity", "true",
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"Enable Density instructions">;
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def HasDensity : Predicate<"Subtarget->hasDensity()">,
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AssemblerPredicate<(all_of FeatureDensity)>;
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//===----------------------------------------------------------------------===//
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// Xtensa supported processors.
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//===----------------------------------------------------------------------===//
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class Proc<string Name, list<SubtargetFeature> Features>
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: Processor<Name, NoItineraries, Features>;
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def : Proc<"generic", []>;
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//===----------------------------------------------------------------------===//
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// Register File Description
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//===----------------------------------------------------------------------===//
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include "XtensaRegisterInfo.td"
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//===----------------------------------------------------------------------===//
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// Instruction Descriptions
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//===----------------------------------------------------------------------===//
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include "XtensaInstrInfo.td"
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def XtensaInstrInfo : InstrInfo;
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//===----------------------------------------------------------------------===//
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// Target Declaration
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//===----------------------------------------------------------------------===//
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def XtensaAsmParser : AsmParser {
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let ShouldEmitMatchRegisterAltName = 1;
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}
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def XtensaInstPrinter : AsmWriter {
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string AsmWriterClassName = "InstPrinter";
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}
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def Xtensa : Target {
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let InstructionSet = XtensaInstrInfo;
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let AssemblyWriters = [XtensaInstPrinter];
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let AssemblyParsers = [XtensaAsmParser];
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}
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