72 lines
1.6 KiB
Text
72 lines
1.6 KiB
Text
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=riscv32 -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
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# RUN: | FileCheck -check-prefix=RV32I %s
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---
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name: virt_to_phys
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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; RV32I-LABEL: name: virt_to_phys
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; RV32I: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1
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; RV32I-NEXT: $x10 = COPY [[ADDI]]
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; RV32I-NEXT: PseudoRET implicit $x10
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%0:gprb(s32) = G_CONSTANT i32 1
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$x10 = COPY %0(s32)
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PseudoRET implicit $x10
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...
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---
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name: phys_to_phys
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $x10, $x11
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; RV32I-LABEL: name: phys_to_phys
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; RV32I: liveins: $x10, $x11
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; RV32I-NEXT: {{ $}}
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; RV32I-NEXT: $x10 = COPY $x11
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; RV32I-NEXT: PseudoRET implicit $x10
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$x10 = COPY $x11
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PseudoRET implicit $x10
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...
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---
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name: virt_to_virt
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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; RV32I-LABEL: name: virt_to_virt
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; RV32I: PseudoRET
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%0:gprb(s32) = G_CONSTANT i32 1
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%1:gprb(s32) = COPY %0(s32)
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PseudoRET
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...
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---
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name: phys_to_virt
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $x10
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; RV32I-LABEL: name: phys_to_virt
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; RV32I: liveins: $x10
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; RV32I-NEXT: {{ $}}
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; RV32I-NEXT: PseudoRET
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%0:gprb(s32) = COPY $x10
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PseudoRET
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...
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