155 lines
8 KiB
MLIR
155 lines
8 KiB
MLIR
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// RUN: mlir-opt %s -allocate-arm-sme-tiles -split-input-file -verify-diagnostics | \
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// RUN: FileCheck %s --check-prefix=AFTER-TILE-ALLOC
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// RUN: mlir-opt %s -allocate-arm-sme-tiles -convert-arm-sme-to-llvm -canonicalize -cse \
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// RUN: -split-input-file -verify-diagnostics | \
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// RUN: FileCheck %s --check-prefix=AFTER-LLVM-LOWERING
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/// Checks tile spill/reloads are inserted around in-memory tiles (i.e. tiles
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/// that were not assigned a physical SME tile).
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///
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/// These spills are currently very naive and will spill/reload entire tiles
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/// around ArmSME ops.
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///
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/// The general pattern is:
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///
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/// During tile allocation if there's not a physical tile ID available an op
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/// will be assigned an in-memory tile ID (which is a tile ID >= 16).
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///
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/// Example:
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///
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/// arm_sme.zero : vector<[8]x[8]xi16>
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///
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/// Becomes:
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///
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/// arm_sme.zero { tile_id = 16 } : vector<[8]x[8]xi16>
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///
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/// This works like normal until the final lowering to LLVM, where spills and
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/// reloads will be inserted around uses of in-memory tiles.
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///
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/// So the above example becomes:
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///
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/// // Placed at the top of the function:
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/// %tileAlloca = memref.alloca(%svl_h, %svl_h) : memref<?x?xi16>
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///
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/// Then around the op:
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///
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/// // Swap contents of %tileAlloca and tile 0
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/// scf.for %sliceIdx ...
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/// %currentSlice = arm_sme.intr.read.horiz {tile_id = 0}
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/// arm_sme.intr.ld1h.horiz %tileAlloca[%sliceIdx, %c0] {tile_id = 0}
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/// vector.store %currentSlice, %tileAlloca[%sliceIdx, %c0]
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/// // Execute the op using tile 0
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/// arm_sme.intr.zero
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/// // Swap contents of %tileAlloca and tile 0
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/// scf.for %sliceIdx ...
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/// %currentSlice = arm_sme.intr.read.horiz {tile_id = 0}
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/// arm_sme.intr.ld1h.horiz %tileAlloca[%sliceIdx, %c0] {tile_id = 0}
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/// vector.store %currentSlice, %tileAlloca[%sliceIdx, %c0]
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///
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// -----
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/// Note: In this example loads into ZA are inserted before the zero instruction.
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/// These are obviously redundant, but there's no checks to avoid this.
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func.func @use_too_many_tiles() {
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%0 = arm_sme.zero : vector<[4]x[4]xi32>
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%1 = arm_sme.zero : vector<[4]x[4]xi32>
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// expected-warning @below {{failed to allocate SME virtual tile to operation, all tile operations will go through memory, expect degraded performance}}
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%2 = arm_sme.zero : vector<[8]x[8]xi16>
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return
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}
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// AFTER-TILE-ALLOC-LABEL: @use_too_many_tiles
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// AFTER-TILE-ALLOC: arm_sme.zero
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// AFTER-TILE-ALLOC-SAME: tile_id = 0
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// AFTER-TILE-ALLOC: arm_sme.zero
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// AFTER-TILE-ALLOC-SAME: tile_id = 1
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// AFTER-TILE-ALLOC: arm_sme.zero
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// AFTER-TILE-ALLOC-SAME: tile_id = 16
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// AFTER-LLVM-LOWERING-LABEL: @use_too_many_tiles
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// AFTER-LLVM-LOWERING-DAG: %[[C0:.*]] = arith.constant 0 : index
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// AFTER-LLVM-LOWERING-DAG: %[[C1:.*]] = arith.constant 1 : index
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// AFTER-LLVM-LOWERING-DAG: %[[C8:.*]] = arith.constant 8 : index
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// AFTER-LLVM-LOWERING-DAG: %[[VSCALE:.*]] = vector.vscale
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// AFTER-LLVM-LOWERING-DAG: %[[SVL_H:.*]] = arith.muli %[[VSCALE]], %[[C8]] : index
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// AFTER-LLVM-LOWERING-DAG: %[[TILE_ALLOCA:.*]] = memref.alloca(%[[SVL_H]], %[[SVL_H]])
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// AFTER-LLVM-LOWERING-SAME: {arm_sme.in_memory_tile_id = 16 : i32} : memref<?x?xi16>
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//
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// AFTER-LLVM-LOWERING-NOT: scf.for
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// Note: 17 is the mask for the 32-bit tile 0.
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// AFTER-LLVM-LOWERING: "arm_sme.intr.zero"() <{tile_mask = 17 : i32}>
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//
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// AFTER-LLVM-LOWERING-NOT: scf.for
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// Note: 34 is the mask for the 32-bit tile 1.
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// AFTER-LLVM-LOWERING: "arm_sme.intr.zero"() <{tile_mask = 34 : i32}>
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//
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// AFTER-LLVM-LOWERING: scf.for
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// AFTER-LLVM-LOWERING-SAME: %[[C0]] to %[[SVL_H]] step %[[C1]] {
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// AFTER-LLVM-LOWERING: %[[MEM_DESC:.*]] = builtin.unrealized_conversion_cast %[[TILE_ALLOCA]]
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// AFTER-LLVM-LOWERING: %[[BASE_PTR:.*]] = llvm.extractvalue %[[MEM_DESC]][1]
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// AFTER-LLVM-LOWERING: %[[SLICE_PTR:.*]] = llvm.getelementptr %[[BASE_PTR]]
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// AFTER-LLVM-LOWERING: %[[SLICE:.*]] = "arm_sme.intr.read.horiz"{{.*}} <{tile_id = 0 : i32}>
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// AFTER-LLVM-LOWERING-NEXT: "arm_sme.intr.ld1h.horiz"({{.*}}, %[[SLICE_PTR]], {{.*}}) <{tile_id = 0 : i32}>
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// AFTER-LLVM-LOWERING-NEXT: vector.store %[[SLICE]], %[[TILE_ALLOCA]]
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// AFTER-LLVM-LOWERING-NEXT: }
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// Note: 85 is the mask for the 16-bit tile 0.
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// AFTER-LLVM-LOWERING: "arm_sme.intr.zero"() <{tile_mask = 85 : i32}>
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// AFTER-LLVM-LOWERING: scf.for
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// AFTER-LLVM-LOWERING-SAME: %[[C0]] to %[[SVL_H]] step %[[C1]] {
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// AFTER-LLVM-LOWERING: %[[MEM_DESC:.*]] = builtin.unrealized_conversion_cast %[[TILE_ALLOCA]]
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// AFTER-LLVM-LOWERING: %[[BASE_PTR:.*]] = llvm.extractvalue %[[MEM_DESC]][1]
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// AFTER-LLVM-LOWERING: %[[SLICE_PTR:.*]] = llvm.getelementptr %[[BASE_PTR]]
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// AFTER-LLVM-LOWERING: %[[SLICE:.*]] = "arm_sme.intr.read.horiz"{{.*}} <{tile_id = 0 : i32}>
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// AFTER-LLVM-LOWERING-NEXT: "arm_sme.intr.ld1h.horiz"({{.*}}, %[[SLICE_PTR]], {{.*}}) <{tile_id = 0 : i32}>
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// AFTER-LLVM-LOWERING-NEXT: vector.store %[[SLICE]], %[[TILE_ALLOCA]]
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// AFTER-LLVM-LOWERING-NEXT: }
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// -----
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/// Note: In this example an entire tile swap is inserted before/after the
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/// `arm_sme.load_tile_slice` operation. Really, this only needs to spill a
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/// single tile slice (and can omit the initial load, like in the previous example).
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func.func @very_excessive_spills(%memref : memref<?x?xf32>) -> vector<[4]x[4]xf32> {
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%useAllTiles = arm_sme.get_tile : vector<[16]x[16]xi8>
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%c0 = arith.constant 0 : index
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// expected-warning @below {{failed to allocate SME virtual tile to operation, all tile operations will go through memory, expect degraded performance}}
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%tile = arm_sme.get_tile : vector<[4]x[4]xf32>
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%mask = vector.constant_mask [4] : vector<[4]xi1>
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%loadSlice = arm_sme.load_tile_slice %memref[%c0, %c0], %mask, %tile, %c0 : memref<?x?xf32>, vector<[4]xi1>, vector<[4]x[4]xf32>
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return %loadSlice : vector<[4]x[4]xf32>
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}
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// AFTER-TILE-ALLOC-LABEL: @very_excessive_spills
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// AFTER-TILE-ALLOC: arm_sme.get_tile
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// AFTER-TILE-ALLOC-SAME: tile_id = 0
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// AFTER-TILE-ALLOC: arm_sme.load_tile_slice
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// AFTER-TILE-ALLOC-SAME: tile_id = 16
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// AFTER-LLVM-LOWERING-LABEL: @very_excessive_spills
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// AFTER-LLVM-LOWERING-DAG: %[[C0:.*]] = arith.constant 0 : index
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// AFTER-LLVM-LOWERING-DAG: %[[C1:.*]] = arith.constant 1 : index
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// AFTER-LLVM-LOWERING-DAG: %[[C4:.*]] = arith.constant 4 : index
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// AFTER-LLVM-LOWERING-DAG: %[[VSCALE:.*]] = vector.vscale
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// AFTER-LLVM-LOWERING-DAG: %[[SVL_S:.*]] = arith.muli %[[VSCALE]], %[[C4]] : index
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// AFTER-LLVM-LOWERING-DAG: %[[TILE_ALLOCA:.*]] = memref.alloca(%[[SVL_S]], %[[SVL_S]])
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// AFTER-LLVM-LOWERING-SAME: {arm_sme.in_memory_tile_id = 16 : i32} : memref<?x?xf32>
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//
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// AFTER-LLVM-LOWERING: scf.for
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// AFTER-LLVM-LOWERING-SAME: %[[C0]] to %[[SVL_S]] step %[[C1]] {
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// AFTER-LLVM-LOWERING: %[[MEM_DESC:.*]] = builtin.unrealized_conversion_cast %[[TILE_ALLOCA]]
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// AFTER-LLVM-LOWERING: %[[BASE_PTR:.*]] = llvm.extractvalue %[[MEM_DESC]][1]
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// AFTER-LLVM-LOWERING: %[[SLICE_PTR:.*]] = llvm.getelementptr %[[BASE_PTR]]
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// AFTER-LLVM-LOWERING: %[[SLICE:.*]] = "arm_sme.intr.read.horiz"{{.*}} <{tile_id = 0 : i32}>
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// AFTER-LLVM-LOWERING-NEXT: "arm_sme.intr.ld1w.horiz"({{.*}}, %[[SLICE_PTR]], {{.*}}) <{tile_id = 0 : i32}>
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// AFTER-LLVM-LOWERING-NEXT: vector.store %[[SLICE]], %[[TILE_ALLOCA]]
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// AFTER-LLVM-LOWERING-NEXT: }
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// AFTER-LLVM-LOWERING: "arm_sme.intr.ld1w.horiz"{{.*}} <{tile_id = 0 : i32}>
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// AFTER-LLVM-LOWERING: scf.for
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// AFTER-LLVM-LOWERING-SAME: %[[C0]] to %[[SVL_S]] step %[[C1]] {
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// AFTER-LLVM-LOWERING: %[[MEM_DESC:.*]] = builtin.unrealized_conversion_cast %[[TILE_ALLOCA]]
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// AFTER-LLVM-LOWERING: %[[BASE_PTR:.*]] = llvm.extractvalue %[[MEM_DESC]][1]
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// AFTER-LLVM-LOWERING: %[[SLICE_PTR:.*]] = llvm.getelementptr %[[BASE_PTR]]
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// AFTER-LLVM-LOWERING: %[[SLICE:.*]] = "arm_sme.intr.read.horiz"{{.*}} <{tile_id = 0 : i32}>
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// AFTER-LLVM-LOWERING-NEXT: "arm_sme.intr.ld1w.horiz"({{.*}}, %[[SLICE_PTR]], {{.*}}) <{tile_id = 0 : i32}>
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// AFTER-LLVM-LOWERING-NEXT: vector.store %[[SLICE]], %[[TILE_ALLOCA]]
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// AFTER-LLVM-LOWERING-NEXT: }
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