35 lines
998 B
C
35 lines
998 B
C
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//===- AMDGPUGlobalISelUtils -------------------------------------*- C++ -*-==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUGLOBALISELUTILS_H
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#define LLVM_LIB_TARGET_AMDGPU_AMDGPUGLOBALISELUTILS_H
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#include "llvm/CodeGen/Register.h"
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#include <utility>
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namespace llvm {
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class MachineRegisterInfo;
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class GCNSubtarget;
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class GISelKnownBits;
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class LLT;
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namespace AMDGPU {
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/// Returns base register and constant offset.
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std::pair<Register, unsigned>
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getBaseWithConstantOffset(MachineRegisterInfo &MRI, Register Reg,
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GISelKnownBits *KnownBits = nullptr,
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bool CheckNUW = false);
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bool hasAtomicFaddRtnForTy(const GCNSubtarget &Subtarget, const LLT &Ty);
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}
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}
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#endif
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