244 lines
9.9 KiB
TableGen
244 lines
9.9 KiB
TableGen
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//===-- M68kInstrFormats.td - M68k Instruction Formats -----*- tablegen -*-===//
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// The LLVM Compiler Infrastructure
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file contains M68k instruction formats.
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///
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/// Since M68k has quite a lot memory addressing modes there are more
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/// instruction prefixes than just i, r and m:
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/// TSF Since Form Letter Description
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/// 00 M68000 Dn or An r any register
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/// 01 M68000 Dn d data register direct
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/// 02 M68000 An a address register direct
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/// 03 M68000 (An) j address register indirect
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/// 04 M68000 (An)+ o address register indirect with postincrement
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/// 05 M68000 -(An) e address register indirect with predecrement
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/// 06 M68000 (d16,An) p address register indirect with displacement
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/// 10 M68000 (d8,An,Xn.L) f address register indirect with index and scale = 1
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/// 07 M68000 (d8,An,Xn.W) F address register indirect with index and scale = 1
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/// 12 M68020 (d8,An,Xn.L,SCALE) g address register indirect with index
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/// 11 M68020 (d8,An,Xn.W,SCALE) G address register indirect with index
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/// 14 M68020 ([bd,An],Xn.L,SCALE,od) u memory indirect postindexed mode
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/// 13 M68020 ([bd,An],Xn.W,SCALE,od) U memory indirect postindexed mode
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/// 16 M68020 ([bd,An,Xn.L,SCALE],od) v memory indirect preindexed mode
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/// 15 M68020 ([bd,An,Xn.W,SCALE],od) V memory indirect preindexed mode
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/// 20 M68000 abs.L b absolute long address
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/// 17 M68000 abs.W B absolute short address
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/// 21 M68000 (d16,PC) q program counter with displacement
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/// 23 M68000 (d8,PC,Xn.L) k program counter with index and scale = 1
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/// 22 M68000 (d8,PC,Xn.W) K program counter with index and scale = 1
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/// 25 M68020 (d8,PC,Xn.L,SCALE) l program counter with index
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/// 24 M68020 (d8,PC,Xn.W,SCALE) L program counter with index
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/// 27 M68020 ([bd,PC],Xn.L,SCALE,od) x program counter memory indirect postindexed mode
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/// 26 M68020 ([bd,PC],Xn.W,SCALE,od) X program counter memory indirect postindexed mode
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/// 31 M68020 ([bd,PC,Xn.L,SCALE],od) y program counter memory indirect preindexed mode
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/// 30 M68020 ([bd,PC,Xn.W,SCALE],od) Y program counter memory indirect preindexed mode
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/// 32 M68000 #immediate i immediate data
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///
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/// NOTE that long form is always lowercase, word variants are capitalized
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///
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/// Operand can be qualified with size where appropriate to force a particular
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/// instruction encoding, e.g.:
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/// (i8,An,Xn.W) f8 1 extension word
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/// (i16,An,Xn.W) f16 2 extension words
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/// (i32,An,Xn.W) f32 3 extension words
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///
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/// Form without size qualifier will adapt to operand size automatically, e.g.:
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/// (i,An,Xn.W) f 1, 2 or 3 extension words
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///
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/// Some forms already imply a particular size of their operands, e.g.:
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/// (i,An) p 1 extension word and i is 16bit
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///
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/// Operand order follows x86 Intel order(destination before source), e.g.:
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/// MOV8df MOVE (4,A0,D0), D1
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///
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/// Number after instruction mnemonics determines the size of the data
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///
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//===----------------------------------------------------------------------===//
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/// ??? Is it possible to use this stuff for disassembling?
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/// NOTE 1: In case of conditional beads(DA, DAReg), cond part is able to
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/// consume any bit, though a more general instructions must be chosen, e.g.
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/// d -> r, a -> r
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//===----------------------------------------------------------------------===//
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// Encoding primitives
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//===----------------------------------------------------------------------===//
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class MxEncMemOp {
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dag EA = (ascend);
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dag Supplement = (ascend);
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}
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class MxEncBriefExt<string reg_opnd, string disp_opnd,
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bit size_w_l = false, int scale = 1,
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string disp_encoder = ""> {
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dag Value = (descend
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// D/A + REGISTER
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(operand "$"#reg_opnd, 4),
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// W/L
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size_w_l,
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// SCALE
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!cond(
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!eq(scale, 1) : 0b00,
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!eq(scale, 2) : 0b01,
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!eq(scale, 4) : 0b10,
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!eq(scale, 8) : 0b11
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),
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0b0,
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// Displacement
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(operand "$"#disp_opnd, 8, (encoder disp_encoder))
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);
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}
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class MxEncAddrMode_d<string reg_opnd> : MxEncMemOp {
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let EA = (descend /*MODE*/0b000,
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/*REGISTER*/(operand "$"#reg_opnd, 3));
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}
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class MxEncAddrMode_a<string reg_opnd> : MxEncMemOp {
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let EA = (descend /*MODE*/0b001,
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/*REGISTER*/(operand "$"#reg_opnd, 3));
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}
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class MxEncAddrMode_r<string reg_opnd> : MxEncMemOp {
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let EA = (descend /*MODE without the last bit*/0b00,
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/*REGISTER with D/A bit*/(operand "$"#reg_opnd, 4));
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}
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class MxEncAddrMode_k<string opnd_name> : MxEncMemOp {
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let EA = (descend /*MODE*/0b111,
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/*REGISTER*/0b011);
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let Supplement = MxEncBriefExt<opnd_name#".index", opnd_name#".disp",
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/*W/L*/true, /*SCALE*/1,
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"encodePCRelImm<8>">.Value;
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}
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class MxEncAddrMode_q<string opnd_name> : MxEncMemOp {
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let EA = (descend /*MODE*/0b111,
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/*REGISTER*/0b010);
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// 16-bit Displacement
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let Supplement = (operand "$"#opnd_name, 16,
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(encoder "encodePCRelImm<16>"));
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}
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class MxEncAddrMode_p<string opnd_name> : MxEncMemOp {
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let EA = (descend /*MODE*/0b101,
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/*REGISTER*/(operand "$"#opnd_name#".reg", 3));
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// 16-bit Displacement
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let Supplement = (operand "$"#opnd_name#".disp", 16,
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(encoder "encodeRelocImm<16>"));
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}
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class MxEncAddrMode_f<string opnd_name> : MxEncMemOp {
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let EA = (descend /*MODE*/0b110,
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/*REGISTER*/(operand "$"#opnd_name#".reg", 3));
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let Supplement = MxEncBriefExt<opnd_name#".index", opnd_name#".disp",
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/*W/L*/true, /*SCALE*/1,
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"encodeRelocImm<8>">.Value;
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}
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class MxEncAddrMode_j<string reg_opnd> : MxEncMemOp {
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let EA = (descend /*MODE*/0b010,
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/*REGISTER*/(operand "$"#reg_opnd, 3));
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}
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class MxEncAddrMode_i<string opnd_name, int size> : MxEncMemOp {
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let EA = (descend /*MODE*/0b111,
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/*REGISTER*/0b100);
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// Immediate
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let Supplement =
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!cond(
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!eq(size, 8) : (descend 0b00000000, (operand "$"#opnd_name, 8,
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(encoder "encodeRelocImm<8>"))),
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!eq(size, 16) : (operand "$"#opnd_name, 16,
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(encoder "encodeRelocImm<16>")),
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!eq(size, 32) : (operand "$"#opnd_name, 32,
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(encoder "encodeRelocImm<32>"),
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(decoder "DecodeImm32"))
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);
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}
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// abs.W -> size_w_l = false
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// abs.L -> size_w_l = true
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class MxEncAddrMode_abs<string opnd_name, bit size_w_l = false> : MxEncMemOp {
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let EA = (descend /*MODE*/0b111,
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// Wrap the REGISTER part in another dag to make sure
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// the dag assigned to EA only has two arguments. Such
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// that it's easier for MOV instructions to reverse
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// on its destination part.
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/*REGISTER*/(descend 0b00, size_w_l));
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// Absolute address
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let Supplement = !if(size_w_l,
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// abs.L
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(operand "$"#opnd_name, 32, (encoder "encodeRelocImm<32>"),
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(decoder "DecodeImm32")),
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// abs.W
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(operand "$"#opnd_name, 16, (encoder "encodeRelocImm<16>"))
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);
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}
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class MxEncAddrMode_o<string reg_opnd> : MxEncMemOp {
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let EA = (descend /*MODE*/0b011,
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/*REGISTER*/(operand "$"#reg_opnd, 3));
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}
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class MxEncAddrMode_e<string reg_opnd> : MxEncMemOp {
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let EA = (descend /*MODE*/0b100,
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/*REGISTER*/(operand "$"#reg_opnd, 3));
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}
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class MxEncSize<bits<2> value> {
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bits<2> Value = value;
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}
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def MxEncSize8 : MxEncSize<0b00>;
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def MxEncSize16 : MxEncSize<0b01>;
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def MxEncSize32 : MxEncSize<0b10>;
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def MxEncSize64 : MxEncSize<0b11>;
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// M68k INSTRUCTION. Most instructions specify the location of an operand by
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// using the effective address field in the operation word. The effective address
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// is composed of two 3-bit fields: the mode field and the register field. The
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// value in the mode field selects the different address modes. The register
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// field contains the number of a register. The effective address field may
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// require additional information to fully specify the operand. This additional
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// information, called the effective address extension, is contained in the
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// following word or words and is considered part of the instruction. The
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// effective address modes are grouped into three categories: register direct,
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// memory addressing, and special.
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class MxInst<dag outs, dag ins,
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string asmStr = "",
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list<dag> pattern = [],
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InstrItinClass itin = NoItinerary>
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: Instruction {
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let Namespace = "M68k";
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let OutOperandList = outs;
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let InOperandList = ins;
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let AsmString = asmStr;
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let Pattern = pattern;
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let Itinerary = itin;
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dag Inst = (ascend);
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// Number of bytes
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let Size = 0;
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let UseLogicalOperandMappings = 1;
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}
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// M68k PSEUDO INSTRUCTION
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class MxPseudo<dag outs, dag ins, list<dag> pattern = []>
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: MxInst<outs, ins, "; error: this should not be emitted", pattern> {
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let isPseudo = 1;
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}
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