228 lines
9.4 KiB
C++
228 lines
9.4 KiB
C++
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//===-- SystemZMCCodeEmitter.cpp - Convert SystemZ code to machine code ---===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the SystemZMCCodeEmitter class.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/SystemZMCFixups.h"
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#include "MCTargetDesc/SystemZMCTargetDesc.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/MC/MCCodeEmitter.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCFixup.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/ErrorHandling.h"
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#include <cassert>
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#include <cstdint>
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using namespace llvm;
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#define DEBUG_TYPE "mccodeemitter"
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namespace {
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class SystemZMCCodeEmitter : public MCCodeEmitter {
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const MCInstrInfo &MCII;
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MCContext &Ctx;
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public:
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SystemZMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
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: MCII(MCII), Ctx(Ctx) {}
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~SystemZMCCodeEmitter() override = default;
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// OVerride MCCodeEmitter.
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void encodeInstruction(const MCInst &MI, SmallVectorImpl<char> &CB,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const override;
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private:
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// Automatically generated by TableGen.
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uint64_t getBinaryCodeForInstr(const MCInst &MI,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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uint32_t getOperandBitOffset(const MCInst &MI, unsigned OpNum,
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const MCSubtargetInfo &STI) const;
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// Called by the TableGen code to get the binary encoding of operand
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// MO in MI. Fixups is the list of fixups against MI.
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uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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// Return the encoded immediate value for the OpNum operand. If it is a
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// symbol, add a fixup for it and return 0.
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template <SystemZ::FixupKind Kind>
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uint64_t getImmOpValue(const MCInst &MI, unsigned OpNum,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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// Called by the TableGen code to get the binary encoding of a length value.
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// Length values are encoded by subtracting 1 from the actual value.
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template <SystemZ::FixupKind Kind>
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uint64_t getLenEncoding(const MCInst &MI, unsigned OpNum,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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// Operand OpNum of MI needs a PC-relative fixup of kind Kind at
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// Offset bytes from the start of MI. Add the fixup to Fixups
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// and return the in-place addend, which since we're a RELA target
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// is always 0. If AllowTLS is true and optional operand OpNum + 1
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// is present, also emit a TLS call fixup for it.
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uint64_t getPCRelEncoding(const MCInst &MI, unsigned OpNum,
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SmallVectorImpl<MCFixup> &Fixups,
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unsigned Kind, int64_t Offset,
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bool AllowTLS) const;
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uint64_t getPC16DBLEncoding(const MCInst &MI, unsigned OpNum,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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return getPCRelEncoding(MI, OpNum, Fixups,
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SystemZ::FK_390_PC16DBL, 2, false);
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}
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uint64_t getPC32DBLEncoding(const MCInst &MI, unsigned OpNum,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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return getPCRelEncoding(MI, OpNum, Fixups,
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SystemZ::FK_390_PC32DBL, 2, false);
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}
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uint64_t getPC16DBLTLSEncoding(const MCInst &MI, unsigned OpNum,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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return getPCRelEncoding(MI, OpNum, Fixups,
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SystemZ::FK_390_PC16DBL, 2, true);
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}
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uint64_t getPC32DBLTLSEncoding(const MCInst &MI, unsigned OpNum,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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return getPCRelEncoding(MI, OpNum, Fixups,
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SystemZ::FK_390_PC32DBL, 2, true);
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}
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uint64_t getPC12DBLBPPEncoding(const MCInst &MI, unsigned OpNum,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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return getPCRelEncoding(MI, OpNum, Fixups,
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SystemZ::FK_390_PC12DBL, 1, false);
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}
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uint64_t getPC16DBLBPPEncoding(const MCInst &MI, unsigned OpNum,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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return getPCRelEncoding(MI, OpNum, Fixups,
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SystemZ::FK_390_PC16DBL, 4, false);
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}
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uint64_t getPC24DBLBPPEncoding(const MCInst &MI, unsigned OpNum,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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return getPCRelEncoding(MI, OpNum, Fixups,
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SystemZ::FK_390_PC24DBL, 3, false);
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}
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};
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} // end anonymous namespace
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void SystemZMCCodeEmitter::encodeInstruction(const MCInst &MI,
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SmallVectorImpl<char> &CB,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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uint64_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
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unsigned Size = MCII.get(MI.getOpcode()).getSize();
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// Big-endian insertion of Size bytes.
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unsigned ShiftValue = (Size * 8) - 8;
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for (unsigned I = 0; I != Size; ++I) {
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CB.push_back(uint8_t(Bits >> ShiftValue));
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ShiftValue -= 8;
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}
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}
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uint64_t SystemZMCCodeEmitter::
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getMachineOpValue(const MCInst &MI, const MCOperand &MO,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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if (MO.isReg())
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return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
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// SystemZAsmParser::parseAnyRegister() produces KindImm when registers are
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// specified as integers.
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if (MO.isImm())
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return static_cast<uint64_t>(MO.getImm());
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llvm_unreachable("Unexpected operand type!");
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}
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template <SystemZ::FixupKind Kind>
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uint64_t SystemZMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNum,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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const MCOperand &MO = MI.getOperand(OpNum);
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if (MO.isImm())
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return static_cast<uint64_t>(MO.getImm());
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if (MO.isExpr()) {
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unsigned MIBitSize = MCII.get(MI.getOpcode()).getSize() * 8;
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uint32_t RawBitOffset = getOperandBitOffset(MI, OpNum, STI);
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unsigned OpBitSize =
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SystemZ::MCFixupKindInfos[Kind - FirstTargetFixupKind].TargetSize;
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uint32_t BitOffset = MIBitSize - RawBitOffset - OpBitSize;
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Fixups.push_back(MCFixup::create(BitOffset >> 3, MO.getExpr(),
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(MCFixupKind)Kind, MI.getLoc()));
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assert(Fixups.size() <= 2 && "More than two memory operands in MI?");
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return 0;
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}
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llvm_unreachable("Unexpected operand type!");
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}
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template <SystemZ::FixupKind Kind>
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uint64_t
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SystemZMCCodeEmitter::getLenEncoding(const MCInst &MI, unsigned OpNum,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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return getImmOpValue<Kind>(MI, OpNum, Fixups, STI) - 1;
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}
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uint64_t
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SystemZMCCodeEmitter::getPCRelEncoding(const MCInst &MI, unsigned OpNum,
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SmallVectorImpl<MCFixup> &Fixups,
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unsigned Kind, int64_t Offset,
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bool AllowTLS) const {
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SMLoc Loc = MI.getLoc();
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const MCOperand &MO = MI.getOperand(OpNum);
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const MCExpr *Expr;
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if (MO.isImm())
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Expr = MCConstantExpr::create(MO.getImm() + Offset, Ctx);
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else {
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Expr = MO.getExpr();
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if (Offset) {
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// The operand value is relative to the start of MI, but the fixup
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// is relative to the operand field itself, which is Offset bytes
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// into MI. Add Offset to the relocation value to cancel out
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// this difference.
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const MCExpr *OffsetExpr = MCConstantExpr::create(Offset, Ctx);
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Expr = MCBinaryExpr::createAdd(Expr, OffsetExpr, Ctx);
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}
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}
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Fixups.push_back(MCFixup::create(Offset, Expr, (MCFixupKind)Kind, Loc));
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// Output the fixup for the TLS marker if present.
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if (AllowTLS && OpNum + 1 < MI.getNumOperands()) {
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const MCOperand &MOTLS = MI.getOperand(OpNum + 1);
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Fixups.push_back(MCFixup::create(
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0, MOTLS.getExpr(), (MCFixupKind)SystemZ::FK_390_TLS_CALL, Loc));
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}
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return 0;
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}
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#define GET_OPERAND_BIT_OFFSET
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#include "SystemZGenMCCodeEmitter.inc"
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MCCodeEmitter *llvm::createSystemZMCCodeEmitter(const MCInstrInfo &MCII,
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MCContext &Ctx) {
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return new SystemZMCCodeEmitter(MCII, Ctx);
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}
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