537 lines
25 KiB
TableGen
537 lines
25 KiB
TableGen
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// WebAssemblyInstrAtomics.td-WebAssembly Atomic codegen support-*- tablegen -*-
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// WebAssembly Atomic operand code-gen constructs.
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///
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//===----------------------------------------------------------------------===//
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let UseNamedOperandTable = 1 in
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multiclass ATOMIC_I<dag oops_r, dag iops_r, dag oops_s, dag iops_s,
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list<dag> pattern_r, string asmstr_r,
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string asmstr_s, bits<32> atomic_op,
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bit is64 = false> {
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defm "" : I<oops_r, iops_r, oops_s, iops_s, pattern_r, asmstr_r, asmstr_s,
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!or(0xfe00, !and(0xff, atomic_op)), is64>,
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Requires<[HasAtomics]>;
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}
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multiclass ATOMIC_NRI<dag oops, dag iops, list<dag> pattern, string asmstr = "",
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bits<32> atomic_op = -1> {
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defm "" : NRI<oops, iops, pattern, asmstr,
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!or(0xfe00, !and(0xff, atomic_op))>,
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Requires<[HasAtomics]>;
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}
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//===----------------------------------------------------------------------===//
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// Atomic wait / notify
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//===----------------------------------------------------------------------===//
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let hasSideEffects = 1 in {
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defm MEMORY_ATOMIC_NOTIFY_A32 :
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ATOMIC_I<(outs I32:$dst),
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(ins P2Align:$p2align, offset32_op:$off, I32:$addr, I32:$count),
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(outs), (ins P2Align:$p2align, offset32_op:$off), [],
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"memory.atomic.notify \t$dst, ${off}(${addr})${p2align}, $count",
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"memory.atomic.notify \t${off}${p2align}", 0x00, false>;
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defm MEMORY_ATOMIC_NOTIFY_A64 :
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ATOMIC_I<(outs I32:$dst),
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(ins P2Align:$p2align, offset64_op:$off, I64:$addr, I32:$count),
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(outs), (ins P2Align:$p2align, offset64_op:$off), [],
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"memory.atomic.notify \t$dst, ${off}(${addr})${p2align}, $count",
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"memory.atomic.notify \t${off}${p2align}", 0x00, true>;
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let mayLoad = 1 in {
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defm MEMORY_ATOMIC_WAIT32_A32 :
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ATOMIC_I<(outs I32:$dst),
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(ins P2Align:$p2align, offset32_op:$off, I32:$addr, I32:$exp,
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I64:$timeout),
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(outs), (ins P2Align:$p2align, offset32_op:$off), [],
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"memory.atomic.wait32 \t$dst, ${off}(${addr})${p2align}, $exp, $timeout",
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"memory.atomic.wait32 \t${off}${p2align}", 0x01, false>;
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defm MEMORY_ATOMIC_WAIT32_A64 :
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ATOMIC_I<(outs I32:$dst),
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(ins P2Align:$p2align, offset64_op:$off, I64:$addr, I32:$exp,
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I64:$timeout),
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(outs), (ins P2Align:$p2align, offset64_op:$off), [],
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"memory.atomic.wait32 \t$dst, ${off}(${addr})${p2align}, $exp, $timeout",
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"memory.atomic.wait32 \t${off}${p2align}", 0x01, true>;
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defm MEMORY_ATOMIC_WAIT64_A32 :
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ATOMIC_I<(outs I32:$dst),
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(ins P2Align:$p2align, offset32_op:$off, I32:$addr, I64:$exp,
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I64:$timeout),
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(outs), (ins P2Align:$p2align, offset32_op:$off), [],
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"memory.atomic.wait64 \t$dst, ${off}(${addr})${p2align}, $exp, $timeout",
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"memory.atomic.wait64 \t${off}${p2align}", 0x02, false>;
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defm MEMORY_ATOMIC_WAIT64_A64 :
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ATOMIC_I<(outs I32:$dst),
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(ins P2Align:$p2align, offset64_op:$off, I64:$addr, I64:$exp,
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I64:$timeout),
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(outs), (ins P2Align:$p2align, offset64_op:$off), [],
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"memory.atomic.wait64 \t$dst, ${off}(${addr})${p2align}, $exp, $timeout",
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"memory.atomic.wait64 \t${off}${p2align}", 0x02, true>;
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} // mayLoad = 1
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} // hasSideEffects = 1
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def NotifyPat_A32 :
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Pat<(i32 (int_wasm_memory_atomic_notify (AddrOps32 offset32_op:$offset, I32:$addr), I32:$count)),
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(MEMORY_ATOMIC_NOTIFY_A32 0, $offset, $addr, $count)>,
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Requires<[HasAddr32, HasAtomics]>;
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def NotifyPat_A64 :
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Pat<(i32 (int_wasm_memory_atomic_notify (AddrOps64 offset64_op:$offset, I64:$addr), I32:$count)),
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(MEMORY_ATOMIC_NOTIFY_A64 0, $offset, $addr, $count)>,
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Requires<[HasAddr64, HasAtomics]>;
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multiclass WaitPat<ValueType ty, Intrinsic kind, string inst> {
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def WaitPat_A32 :
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Pat<(i32 (kind (AddrOps32 offset32_op:$offset, I32:$addr), ty:$exp, I64:$timeout)),
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(!cast<NI>(inst#_A32) 0, $offset, $addr, $exp, $timeout)>,
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Requires<[HasAddr32, HasAtomics]>;
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def WaitPat_A64 :
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Pat<(i32 (kind (AddrOps64 offset64_op:$offset, I64:$addr), ty:$exp, I64:$timeout)),
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(!cast<NI>(inst#_A64) 0, $offset, $addr, $exp, $timeout)>,
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Requires<[HasAddr64, HasAtomics]>;
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}
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defm : WaitPat<i32, int_wasm_memory_atomic_wait32, "MEMORY_ATOMIC_WAIT32">;
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defm : WaitPat<i64, int_wasm_memory_atomic_wait64, "MEMORY_ATOMIC_WAIT64">;
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//===----------------------------------------------------------------------===//
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// Atomic fences
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//===----------------------------------------------------------------------===//
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// A compiler fence instruction that prevents reordering of instructions.
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let Defs = [ARGUMENTS] in {
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let isPseudo = 1, hasSideEffects = 1 in
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defm COMPILER_FENCE : ATOMIC_NRI<(outs), (ins), [], "compiler_fence">;
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let hasSideEffects = 1 in
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defm ATOMIC_FENCE : ATOMIC_NRI<(outs), (ins i8imm:$flags), [], "atomic.fence",
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0x03>;
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} // Defs = [ARGUMENTS]
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//===----------------------------------------------------------------------===//
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// Atomic loads
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//===----------------------------------------------------------------------===//
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multiclass AtomicLoad<WebAssemblyRegClass rc, string name, int atomic_op> {
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defm "" : WebAssemblyLoad<rc, name, !or(0xfe00, !and(0xff, atomic_op)),
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[HasAtomics]>;
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}
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defm ATOMIC_LOAD_I32 : AtomicLoad<I32, "i32.atomic.load", 0x10>;
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defm ATOMIC_LOAD_I64 : AtomicLoad<I64, "i64.atomic.load", 0x11>;
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// Select loads
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defm : LoadPat<i32, atomic_load_32, "ATOMIC_LOAD_I32">;
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defm : LoadPat<i64, atomic_load_64, "ATOMIC_LOAD_I64">;
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// Extending loads. Note that there are only zero-extending atomic loads, no
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// sign-extending loads.
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defm ATOMIC_LOAD8_U_I32 : AtomicLoad<I32, "i32.atomic.load8_u", 0x12>;
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defm ATOMIC_LOAD16_U_I32 : AtomicLoad<I32, "i32.atomic.load16_u", 0x13>;
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defm ATOMIC_LOAD8_U_I64 : AtomicLoad<I64, "i64.atomic.load8_u", 0x14>;
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defm ATOMIC_LOAD16_U_I64 : AtomicLoad<I64, "i64.atomic.load16_u", 0x15>;
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defm ATOMIC_LOAD32_U_I64 : AtomicLoad<I64, "i64.atomic.load32_u", 0x16>;
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// Fragments for extending loads. These are different from regular loads because
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// the SDNodes are derived from AtomicSDNode rather than LoadSDNode and
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// therefore don't have the extension type field. So instead of matching that,
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// we match the patterns that the type legalizer expands them to.
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// Unlike regular loads, extension to i64 is handled differently than i32.
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// i64 (zext (i8 (atomic_load_8))) gets legalized to
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// i64 (and (i64 (anyext (i32 (atomic_load_8)))), 255)
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// Extension to i32 is elided by SelectionDAG as our atomic loads are
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// zero-extending.
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def zext_aload_8_64 :
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PatFrag<(ops node:$addr),
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(i64 (zext (i32 (atomic_load_8 node:$addr))))>;
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def zext_aload_16_64 :
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PatFrag<(ops node:$addr),
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(i64 (zext (i32 (atomic_load_16 node:$addr))))>;
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def zext_aload_32_64 :
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PatFrag<(ops node:$addr),
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(i64 (zext (i32 (atomic_load_32 node:$addr))))>;
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// We don't have single sext atomic load instructions. So for sext loads, we
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// match bare subword loads (for 32-bit results) and anyext loads (for 64-bit
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// results) and select a zext load; the next instruction will be sext_inreg
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// which is selected by itself.
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def sext_aload_8_64 :
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PatFrag<(ops node:$addr), (anyext (i32 (atomic_load_8 node:$addr)))>;
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def sext_aload_16_64 :
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PatFrag<(ops node:$addr), (anyext (i32 (atomic_load_16 node:$addr)))>;
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// Select zero-extending loads
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defm : LoadPat<i64, zext_aload_8_64, "ATOMIC_LOAD8_U_I64">;
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defm : LoadPat<i64, zext_aload_16_64, "ATOMIC_LOAD16_U_I64">;
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defm : LoadPat<i64, zext_aload_32_64, "ATOMIC_LOAD32_U_I64">;
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// Select sign-extending loads
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defm : LoadPat<i32, atomic_load_8, "ATOMIC_LOAD8_U_I32">;
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defm : LoadPat<i32, atomic_load_16, "ATOMIC_LOAD16_U_I32">;
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defm : LoadPat<i64, sext_aload_8_64, "ATOMIC_LOAD8_U_I64">;
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defm : LoadPat<i64, sext_aload_16_64, "ATOMIC_LOAD16_U_I64">;
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// 32->64 sext load gets selected as i32.atomic.load, i64.extend_i32_s
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//===----------------------------------------------------------------------===//
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// Atomic stores
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//===----------------------------------------------------------------------===//
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multiclass AtomicStore<WebAssemblyRegClass rc, string name, int atomic_op> {
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defm "" : WebAssemblyStore<rc, name, !or(0xfe00, !and(0xff, atomic_op)),
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[HasAtomics]>;
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}
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defm ATOMIC_STORE_I32 : AtomicStore<I32, "i32.atomic.store", 0x17>;
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defm ATOMIC_STORE_I64 : AtomicStore<I64, "i64.atomic.store", 0x18>;
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// We used to need an 'atomic' version of store patterns because store and atomic_store
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// nodes have different operand orders.
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//
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// TODO: This is no longer true and atomic_store and store patterns
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// can be unified.
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multiclass AStorePat<ValueType ty, PatFrag kind, string inst> {
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def : Pat<(kind ty:$val, (AddrOps32 offset32_op:$offset, I32:$addr)),
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(!cast<NI>(inst#_A32) 0, $offset, $addr, $val)>,
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Requires<[HasAddr32, HasAtomics]>;
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def : Pat<(kind ty:$val, (AddrOps64 offset64_op:$offset, I64:$addr)),
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(!cast<NI>(inst#_A64) 0, $offset, $addr, $val)>,
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Requires<[HasAddr64, HasAtomics]>;
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}
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defm : AStorePat<i32, atomic_store_32, "ATOMIC_STORE_I32">;
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defm : AStorePat<i64, atomic_store_64, "ATOMIC_STORE_I64">;
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// Truncating stores.
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defm ATOMIC_STORE8_I32 : AtomicStore<I32, "i32.atomic.store8", 0x19>;
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defm ATOMIC_STORE16_I32 : AtomicStore<I32, "i32.atomic.store16", 0x1a>;
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defm ATOMIC_STORE8_I64 : AtomicStore<I64, "i64.atomic.store8", 0x1b>;
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defm ATOMIC_STORE16_I64 : AtomicStore<I64, "i64.atomic.store16", 0x1c>;
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defm ATOMIC_STORE32_I64 : AtomicStore<I64, "i64.atomic.store32", 0x1d>;
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// Fragments for truncating stores.
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// We don't have single truncating atomic store instructions. For 32-bit
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// instructions, we just need to match bare atomic stores. On the other hand,
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// truncating stores from i64 values are once truncated to i32 first.
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class trunc_astore_64<PatFrag kind> :
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PatFrag<(ops node:$val, node:$addr),
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(kind (i32 (trunc (i64 node:$val))), node:$addr)>;
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def trunc_astore_8_64 : trunc_astore_64<atomic_store_8>;
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def trunc_astore_16_64 : trunc_astore_64<atomic_store_16>;
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def trunc_astore_32_64 : trunc_astore_64<atomic_store_32>;
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// Truncating stores with no constant offset
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defm : AStorePat<i32, atomic_store_8, "ATOMIC_STORE8_I32">;
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defm : AStorePat<i32, atomic_store_16, "ATOMIC_STORE16_I32">;
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defm : AStorePat<i64, trunc_astore_8_64, "ATOMIC_STORE8_I64">;
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defm : AStorePat<i64, trunc_astore_16_64, "ATOMIC_STORE16_I64">;
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defm : AStorePat<i64, trunc_astore_32_64, "ATOMIC_STORE32_I64">;
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//===----------------------------------------------------------------------===//
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// Atomic binary read-modify-writes
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//===----------------------------------------------------------------------===//
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multiclass WebAssemblyBinRMW<WebAssemblyRegClass rc, string name,
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int atomic_op> {
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defm "_A32" :
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ATOMIC_I<(outs rc:$dst),
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(ins P2Align:$p2align, offset32_op:$off, I32:$addr, rc:$val),
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(outs), (ins P2Align:$p2align, offset32_op:$off), [],
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!strconcat(name, "\t$dst, ${off}(${addr})${p2align}, $val"),
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!strconcat(name, "\t${off}${p2align}"), atomic_op, false>;
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defm "_A64" :
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ATOMIC_I<(outs rc:$dst),
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(ins P2Align:$p2align, offset64_op:$off, I64:$addr, rc:$val),
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(outs), (ins P2Align:$p2align, offset64_op:$off), [],
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!strconcat(name, "\t$dst, ${off}(${addr})${p2align}, $val"),
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!strconcat(name, "\t${off}${p2align}"), atomic_op, true>;
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}
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defm ATOMIC_RMW_ADD_I32 : WebAssemblyBinRMW<I32, "i32.atomic.rmw.add", 0x1e>;
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defm ATOMIC_RMW_ADD_I64 : WebAssemblyBinRMW<I64, "i64.atomic.rmw.add", 0x1f>;
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defm ATOMIC_RMW8_U_ADD_I32 :
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WebAssemblyBinRMW<I32, "i32.atomic.rmw8.add_u", 0x20>;
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defm ATOMIC_RMW16_U_ADD_I32 :
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WebAssemblyBinRMW<I32, "i32.atomic.rmw16.add_u", 0x21>;
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defm ATOMIC_RMW8_U_ADD_I64 :
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WebAssemblyBinRMW<I64, "i64.atomic.rmw8.add_u", 0x22>;
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defm ATOMIC_RMW16_U_ADD_I64 :
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WebAssemblyBinRMW<I64, "i64.atomic.rmw16.add_u", 0x23>;
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defm ATOMIC_RMW32_U_ADD_I64 :
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WebAssemblyBinRMW<I64, "i64.atomic.rmw32.add_u", 0x24>;
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defm ATOMIC_RMW_SUB_I32 : WebAssemblyBinRMW<I32, "i32.atomic.rmw.sub", 0x25>;
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defm ATOMIC_RMW_SUB_I64 : WebAssemblyBinRMW<I64, "i64.atomic.rmw.sub", 0x26>;
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defm ATOMIC_RMW8_U_SUB_I32 :
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WebAssemblyBinRMW<I32, "i32.atomic.rmw8.sub_u", 0x27>;
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defm ATOMIC_RMW16_U_SUB_I32 :
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WebAssemblyBinRMW<I32, "i32.atomic.rmw16.sub_u", 0x28>;
|
||
|
|
defm ATOMIC_RMW8_U_SUB_I64 :
|
||
|
|
WebAssemblyBinRMW<I64, "i64.atomic.rmw8.sub_u", 0x29>;
|
||
|
|
defm ATOMIC_RMW16_U_SUB_I64 :
|
||
|
|
WebAssemblyBinRMW<I64, "i64.atomic.rmw16.sub_u", 0x2a>;
|
||
|
|
defm ATOMIC_RMW32_U_SUB_I64 :
|
||
|
|
WebAssemblyBinRMW<I64, "i64.atomic.rmw32.sub_u", 0x2b>;
|
||
|
|
|
||
|
|
defm ATOMIC_RMW_AND_I32 : WebAssemblyBinRMW<I32, "i32.atomic.rmw.and", 0x2c>;
|
||
|
|
defm ATOMIC_RMW_AND_I64 : WebAssemblyBinRMW<I64, "i64.atomic.rmw.and", 0x2d>;
|
||
|
|
defm ATOMIC_RMW8_U_AND_I32 :
|
||
|
|
WebAssemblyBinRMW<I32, "i32.atomic.rmw8.and_u", 0x2e>;
|
||
|
|
defm ATOMIC_RMW16_U_AND_I32 :
|
||
|
|
WebAssemblyBinRMW<I32, "i32.atomic.rmw16.and_u", 0x2f>;
|
||
|
|
defm ATOMIC_RMW8_U_AND_I64 :
|
||
|
|
WebAssemblyBinRMW<I64, "i64.atomic.rmw8.and_u", 0x30>;
|
||
|
|
defm ATOMIC_RMW16_U_AND_I64 :
|
||
|
|
WebAssemblyBinRMW<I64, "i64.atomic.rmw16.and_u", 0x31>;
|
||
|
|
defm ATOMIC_RMW32_U_AND_I64 :
|
||
|
|
WebAssemblyBinRMW<I64, "i64.atomic.rmw32.and_u", 0x32>;
|
||
|
|
|
||
|
|
defm ATOMIC_RMW_OR_I32 : WebAssemblyBinRMW<I32, "i32.atomic.rmw.or", 0x33>;
|
||
|
|
defm ATOMIC_RMW_OR_I64 : WebAssemblyBinRMW<I64, "i64.atomic.rmw.or", 0x34>;
|
||
|
|
defm ATOMIC_RMW8_U_OR_I32 :
|
||
|
|
WebAssemblyBinRMW<I32, "i32.atomic.rmw8.or_u", 0x35>;
|
||
|
|
defm ATOMIC_RMW16_U_OR_I32 :
|
||
|
|
WebAssemblyBinRMW<I32, "i32.atomic.rmw16.or_u", 0x36>;
|
||
|
|
defm ATOMIC_RMW8_U_OR_I64 :
|
||
|
|
WebAssemblyBinRMW<I64, "i64.atomic.rmw8.or_u", 0x37>;
|
||
|
|
defm ATOMIC_RMW16_U_OR_I64 :
|
||
|
|
WebAssemblyBinRMW<I64, "i64.atomic.rmw16.or_u", 0x38>;
|
||
|
|
defm ATOMIC_RMW32_U_OR_I64 :
|
||
|
|
WebAssemblyBinRMW<I64, "i64.atomic.rmw32.or_u", 0x39>;
|
||
|
|
|
||
|
|
defm ATOMIC_RMW_XOR_I32 : WebAssemblyBinRMW<I32, "i32.atomic.rmw.xor", 0x3a>;
|
||
|
|
defm ATOMIC_RMW_XOR_I64 : WebAssemblyBinRMW<I64, "i64.atomic.rmw.xor", 0x3b>;
|
||
|
|
defm ATOMIC_RMW8_U_XOR_I32 :
|
||
|
|
WebAssemblyBinRMW<I32, "i32.atomic.rmw8.xor_u", 0x3c>;
|
||
|
|
defm ATOMIC_RMW16_U_XOR_I32 :
|
||
|
|
WebAssemblyBinRMW<I32, "i32.atomic.rmw16.xor_u", 0x3d>;
|
||
|
|
defm ATOMIC_RMW8_U_XOR_I64 :
|
||
|
|
WebAssemblyBinRMW<I64, "i64.atomic.rmw8.xor_u", 0x3e>;
|
||
|
|
defm ATOMIC_RMW16_U_XOR_I64 :
|
||
|
|
WebAssemblyBinRMW<I64, "i64.atomic.rmw16.xor_u", 0x3f>;
|
||
|
|
defm ATOMIC_RMW32_U_XOR_I64 :
|
||
|
|
WebAssemblyBinRMW<I64, "i64.atomic.rmw32.xor_u", 0x40>;
|
||
|
|
|
||
|
|
defm ATOMIC_RMW_XCHG_I32 :
|
||
|
|
WebAssemblyBinRMW<I32, "i32.atomic.rmw.xchg", 0x41>;
|
||
|
|
defm ATOMIC_RMW_XCHG_I64 :
|
||
|
|
WebAssemblyBinRMW<I64, "i64.atomic.rmw.xchg", 0x42>;
|
||
|
|
defm ATOMIC_RMW8_U_XCHG_I32 :
|
||
|
|
WebAssemblyBinRMW<I32, "i32.atomic.rmw8.xchg_u", 0x43>;
|
||
|
|
defm ATOMIC_RMW16_U_XCHG_I32 :
|
||
|
|
WebAssemblyBinRMW<I32, "i32.atomic.rmw16.xchg_u", 0x44>;
|
||
|
|
defm ATOMIC_RMW8_U_XCHG_I64 :
|
||
|
|
WebAssemblyBinRMW<I64, "i64.atomic.rmw8.xchg_u", 0x45>;
|
||
|
|
defm ATOMIC_RMW16_U_XCHG_I64 :
|
||
|
|
WebAssemblyBinRMW<I64, "i64.atomic.rmw16.xchg_u", 0x46>;
|
||
|
|
defm ATOMIC_RMW32_U_XCHG_I64 :
|
||
|
|
WebAssemblyBinRMW<I64, "i64.atomic.rmw32.xchg_u", 0x47>;
|
||
|
|
|
||
|
|
multiclass BinRMWPat<ValueType ty, PatFrag kind, string inst> {
|
||
|
|
def : Pat<(ty (kind (AddrOps32 offset32_op:$offset, I32:$addr), ty:$val)),
|
||
|
|
(!cast<NI>(inst#_A32) 0, $offset, $addr, $val)>,
|
||
|
|
Requires<[HasAddr32, HasAtomics]>;
|
||
|
|
def : Pat<(ty (kind (AddrOps64 offset64_op:$offset, I64:$addr), ty:$val)),
|
||
|
|
(!cast<NI>(inst#_A64) 0, $offset, $addr, $val)>,
|
||
|
|
Requires<[HasAddr64, HasAtomics]>;
|
||
|
|
}
|
||
|
|
|
||
|
|
// Patterns for various addressing modes.
|
||
|
|
multiclass BinRMWPattern<PatFrag rmw_32, PatFrag rmw_64, string inst_32,
|
||
|
|
string inst_64> {
|
||
|
|
defm : BinRMWPat<i32, rmw_32, inst_32>;
|
||
|
|
defm : BinRMWPat<i64, rmw_64, inst_64>;
|
||
|
|
}
|
||
|
|
|
||
|
|
defm : BinRMWPattern<atomic_load_add_32, atomic_load_add_64,
|
||
|
|
"ATOMIC_RMW_ADD_I32", "ATOMIC_RMW_ADD_I64">;
|
||
|
|
defm : BinRMWPattern<atomic_load_sub_32, atomic_load_sub_64,
|
||
|
|
"ATOMIC_RMW_SUB_I32", "ATOMIC_RMW_SUB_I64">;
|
||
|
|
defm : BinRMWPattern<atomic_load_and_32, atomic_load_and_64,
|
||
|
|
"ATOMIC_RMW_AND_I32", "ATOMIC_RMW_AND_I64">;
|
||
|
|
defm : BinRMWPattern<atomic_load_or_32, atomic_load_or_64,
|
||
|
|
"ATOMIC_RMW_OR_I32", "ATOMIC_RMW_OR_I64">;
|
||
|
|
defm : BinRMWPattern<atomic_load_xor_32, atomic_load_xor_64,
|
||
|
|
"ATOMIC_RMW_XOR_I32", "ATOMIC_RMW_XOR_I64">;
|
||
|
|
defm : BinRMWPattern<atomic_swap_32, atomic_swap_64,
|
||
|
|
"ATOMIC_RMW_XCHG_I32", "ATOMIC_RMW_XCHG_I64">;
|
||
|
|
|
||
|
|
// Truncating & zero-extending binary RMW patterns.
|
||
|
|
// These are combined patterns of truncating store patterns and zero-extending
|
||
|
|
// load patterns above.
|
||
|
|
class zext_bin_rmw_8_32<PatFrag kind> :
|
||
|
|
PatFrag<(ops node:$addr, node:$val), (i32 (kind node:$addr, node:$val))>;
|
||
|
|
class zext_bin_rmw_16_32<PatFrag kind> : zext_bin_rmw_8_32<kind>;
|
||
|
|
class zext_bin_rmw_8_64<PatFrag kind> :
|
||
|
|
PatFrag<(ops node:$addr, node:$val),
|
||
|
|
(zext (i32 (kind node:$addr, (i32 (trunc (i64 node:$val))))))>;
|
||
|
|
class zext_bin_rmw_16_64<PatFrag kind> : zext_bin_rmw_8_64<kind>;
|
||
|
|
class zext_bin_rmw_32_64<PatFrag kind> : zext_bin_rmw_8_64<kind>;
|
||
|
|
|
||
|
|
// Truncating & sign-extending binary RMW patterns.
|
||
|
|
// These are combined patterns of truncating store patterns and sign-extending
|
||
|
|
// load patterns above. We match subword RMWs (for 32-bit) and anyext RMWs (for
|
||
|
|
// 64-bit) and select a zext RMW; the next instruction will be sext_inreg which
|
||
|
|
// is selected by itself.
|
||
|
|
class sext_bin_rmw_8_32<PatFrag kind> :
|
||
|
|
PatFrag<(ops node:$addr, node:$val), (kind node:$addr, node:$val)>;
|
||
|
|
class sext_bin_rmw_16_32<PatFrag kind> : sext_bin_rmw_8_32<kind>;
|
||
|
|
class sext_bin_rmw_8_64<PatFrag kind> :
|
||
|
|
PatFrag<(ops node:$addr, node:$val),
|
||
|
|
(anyext (i32 (kind node:$addr, (i32 (trunc (i64 node:$val))))))>;
|
||
|
|
class sext_bin_rmw_16_64<PatFrag kind> : sext_bin_rmw_8_64<kind>;
|
||
|
|
// 32->64 sext RMW gets selected as i32.atomic.rmw.***, i64.extend_i32_s
|
||
|
|
|
||
|
|
// Patterns for various addressing modes for truncating-extending binary RMWs.
|
||
|
|
multiclass BinRMWTruncExtPattern<
|
||
|
|
PatFrag rmw_8, PatFrag rmw_16, PatFrag rmw_32,
|
||
|
|
string inst8_32, string inst16_32, string inst8_64, string inst16_64, string inst32_64> {
|
||
|
|
// Truncating-extending binary RMWs
|
||
|
|
defm : BinRMWPat<i32, zext_bin_rmw_8_32<rmw_8>, inst8_32>;
|
||
|
|
defm : BinRMWPat<i32, zext_bin_rmw_16_32<rmw_16>, inst16_32>;
|
||
|
|
defm : BinRMWPat<i64, zext_bin_rmw_8_64<rmw_8>, inst8_64>;
|
||
|
|
defm : BinRMWPat<i64, zext_bin_rmw_16_64<rmw_16>, inst16_64>;
|
||
|
|
defm : BinRMWPat<i64, zext_bin_rmw_32_64<rmw_32>, inst32_64>;
|
||
|
|
|
||
|
|
defm : BinRMWPat<i32, sext_bin_rmw_8_32<rmw_8>, inst8_32>;
|
||
|
|
defm : BinRMWPat<i32, sext_bin_rmw_16_32<rmw_16>, inst16_32>;
|
||
|
|
defm : BinRMWPat<i64, sext_bin_rmw_8_64<rmw_8>, inst8_64>;
|
||
|
|
defm : BinRMWPat<i64, sext_bin_rmw_16_64<rmw_16>, inst16_64>;
|
||
|
|
}
|
||
|
|
|
||
|
|
defm : BinRMWTruncExtPattern<
|
||
|
|
atomic_load_add_8, atomic_load_add_16, atomic_load_add_32,
|
||
|
|
"ATOMIC_RMW8_U_ADD_I32", "ATOMIC_RMW16_U_ADD_I32",
|
||
|
|
"ATOMIC_RMW8_U_ADD_I64", "ATOMIC_RMW16_U_ADD_I64", "ATOMIC_RMW32_U_ADD_I64">;
|
||
|
|
defm : BinRMWTruncExtPattern<
|
||
|
|
atomic_load_sub_8, atomic_load_sub_16, atomic_load_sub_32,
|
||
|
|
"ATOMIC_RMW8_U_SUB_I32", "ATOMIC_RMW16_U_SUB_I32",
|
||
|
|
"ATOMIC_RMW8_U_SUB_I64", "ATOMIC_RMW16_U_SUB_I64", "ATOMIC_RMW32_U_SUB_I64">;
|
||
|
|
defm : BinRMWTruncExtPattern<
|
||
|
|
atomic_load_and_8, atomic_load_and_16, atomic_load_and_32,
|
||
|
|
"ATOMIC_RMW8_U_AND_I32", "ATOMIC_RMW16_U_AND_I32",
|
||
|
|
"ATOMIC_RMW8_U_AND_I64", "ATOMIC_RMW16_U_AND_I64", "ATOMIC_RMW32_U_AND_I64">;
|
||
|
|
defm : BinRMWTruncExtPattern<
|
||
|
|
atomic_load_or_8, atomic_load_or_16, atomic_load_or_32,
|
||
|
|
"ATOMIC_RMW8_U_OR_I32", "ATOMIC_RMW16_U_OR_I32",
|
||
|
|
"ATOMIC_RMW8_U_OR_I64", "ATOMIC_RMW16_U_OR_I64", "ATOMIC_RMW32_U_OR_I64">;
|
||
|
|
defm : BinRMWTruncExtPattern<
|
||
|
|
atomic_load_xor_8, atomic_load_xor_16, atomic_load_xor_32,
|
||
|
|
"ATOMIC_RMW8_U_XOR_I32", "ATOMIC_RMW16_U_XOR_I32",
|
||
|
|
"ATOMIC_RMW8_U_XOR_I64", "ATOMIC_RMW16_U_XOR_I64", "ATOMIC_RMW32_U_XOR_I64">;
|
||
|
|
defm : BinRMWTruncExtPattern<
|
||
|
|
atomic_swap_8, atomic_swap_16, atomic_swap_32,
|
||
|
|
"ATOMIC_RMW8_U_XCHG_I32", "ATOMIC_RMW16_U_XCHG_I32",
|
||
|
|
"ATOMIC_RMW8_U_XCHG_I64", "ATOMIC_RMW16_U_XCHG_I64",
|
||
|
|
"ATOMIC_RMW32_U_XCHG_I64">;
|
||
|
|
|
||
|
|
//===----------------------------------------------------------------------===//
|
||
|
|
// Atomic ternary read-modify-writes
|
||
|
|
//===----------------------------------------------------------------------===//
|
||
|
|
|
||
|
|
// TODO LLVM IR's cmpxchg instruction returns a pair of {loaded value, success
|
||
|
|
// flag}. When we use the success flag or both values, we can't make use of i64
|
||
|
|
// truncate/extend versions of instructions for now, which is suboptimal.
|
||
|
|
// Consider adding a pass after instruction selection that optimizes this case
|
||
|
|
// if it is frequent.
|
||
|
|
|
||
|
|
multiclass WebAssemblyTerRMW<WebAssemblyRegClass rc, string name,
|
||
|
|
int atomic_op> {
|
||
|
|
defm "_A32" :
|
||
|
|
ATOMIC_I<(outs rc:$dst),
|
||
|
|
(ins P2Align:$p2align, offset32_op:$off, I32:$addr, rc:$exp,
|
||
|
|
rc:$new_),
|
||
|
|
(outs), (ins P2Align:$p2align, offset32_op:$off), [],
|
||
|
|
!strconcat(name, "\t$dst, ${off}(${addr})${p2align}, $exp, $new_"),
|
||
|
|
!strconcat(name, "\t${off}${p2align}"), atomic_op, false>;
|
||
|
|
defm "_A64" :
|
||
|
|
ATOMIC_I<(outs rc:$dst),
|
||
|
|
(ins P2Align:$p2align, offset64_op:$off, I64:$addr, rc:$exp,
|
||
|
|
rc:$new_),
|
||
|
|
(outs), (ins P2Align:$p2align, offset64_op:$off), [],
|
||
|
|
!strconcat(name, "\t$dst, ${off}(${addr})${p2align}, $exp, $new_"),
|
||
|
|
!strconcat(name, "\t${off}${p2align}"), atomic_op, true>;
|
||
|
|
}
|
||
|
|
|
||
|
|
defm ATOMIC_RMW_CMPXCHG_I32 :
|
||
|
|
WebAssemblyTerRMW<I32, "i32.atomic.rmw.cmpxchg", 0x48>;
|
||
|
|
defm ATOMIC_RMW_CMPXCHG_I64 :
|
||
|
|
WebAssemblyTerRMW<I64, "i64.atomic.rmw.cmpxchg", 0x49>;
|
||
|
|
defm ATOMIC_RMW8_U_CMPXCHG_I32 :
|
||
|
|
WebAssemblyTerRMW<I32, "i32.atomic.rmw8.cmpxchg_u", 0x4a>;
|
||
|
|
defm ATOMIC_RMW16_U_CMPXCHG_I32 :
|
||
|
|
WebAssemblyTerRMW<I32, "i32.atomic.rmw16.cmpxchg_u", 0x4b>;
|
||
|
|
defm ATOMIC_RMW8_U_CMPXCHG_I64 :
|
||
|
|
WebAssemblyTerRMW<I64, "i64.atomic.rmw8.cmpxchg_u", 0x4c>;
|
||
|
|
defm ATOMIC_RMW16_U_CMPXCHG_I64 :
|
||
|
|
WebAssemblyTerRMW<I64, "i64.atomic.rmw16.cmpxchg_u", 0x4d>;
|
||
|
|
defm ATOMIC_RMW32_U_CMPXCHG_I64 :
|
||
|
|
WebAssemblyTerRMW<I64, "i64.atomic.rmw32.cmpxchg_u", 0x4e>;
|
||
|
|
|
||
|
|
multiclass TerRMWPat<ValueType ty, PatFrag kind, string inst> {
|
||
|
|
def : Pat<(ty (kind (AddrOps32 offset32_op:$offset, I32:$addr), ty:$exp, ty:$new)),
|
||
|
|
(!cast<NI>(inst#_A32) 0, $offset, $addr, $exp, $new)>,
|
||
|
|
Requires<[HasAddr32, HasAtomics]>;
|
||
|
|
def : Pat<(ty (kind (AddrOps64 offset64_op:$offset, I64:$addr), ty:$exp, ty:$new)),
|
||
|
|
(!cast<NI>(inst#_A64) 0, $offset, $addr, $exp, $new)>,
|
||
|
|
Requires<[HasAddr64, HasAtomics]>;
|
||
|
|
}
|
||
|
|
|
||
|
|
defm : TerRMWPat<i32, atomic_cmp_swap_32, "ATOMIC_RMW_CMPXCHG_I32">;
|
||
|
|
defm : TerRMWPat<i64, atomic_cmp_swap_64, "ATOMIC_RMW_CMPXCHG_I64">;
|
||
|
|
|
||
|
|
// Truncating & zero-extending ternary RMW patterns.
|
||
|
|
// DAG legalization & optimization before instruction selection may introduce
|
||
|
|
// additional nodes such as anyext or assertzext depending on operand types.
|
||
|
|
class zext_ter_rmw_8_32<PatFrag kind> :
|
||
|
|
PatFrag<(ops node:$addr, node:$exp, node:$new),
|
||
|
|
(i32 (kind node:$addr, node:$exp, node:$new))>;
|
||
|
|
class zext_ter_rmw_16_32<PatFrag kind> : zext_ter_rmw_8_32<kind>;
|
||
|
|
class zext_ter_rmw_8_64<PatFrag kind> :
|
||
|
|
PatFrag<(ops node:$addr, node:$exp, node:$new),
|
||
|
|
(zext (i32 (assertzext (i32 (kind node:$addr,
|
||
|
|
(i32 (trunc (i64 node:$exp))),
|
||
|
|
(i32 (trunc (i64 node:$new))))))))>;
|
||
|
|
class zext_ter_rmw_16_64<PatFrag kind> : zext_ter_rmw_8_64<kind>;
|
||
|
|
class zext_ter_rmw_32_64<PatFrag kind> :
|
||
|
|
PatFrag<(ops node:$addr, node:$exp, node:$new),
|
||
|
|
(zext (i32 (kind node:$addr,
|
||
|
|
(i32 (trunc (i64 node:$exp))),
|
||
|
|
(i32 (trunc (i64 node:$new))))))>;
|
||
|
|
|
||
|
|
// Truncating & sign-extending ternary RMW patterns.
|
||
|
|
// We match subword RMWs (for 32-bit) and anyext RMWs (for 64-bit) and select a
|
||
|
|
// zext RMW; the next instruction will be sext_inreg which is selected by
|
||
|
|
// itself.
|
||
|
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class sext_ter_rmw_8_32<PatFrag kind> :
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PatFrag<(ops node:$addr, node:$exp, node:$new),
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(kind node:$addr, node:$exp, node:$new)>;
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class sext_ter_rmw_16_32<PatFrag kind> : sext_ter_rmw_8_32<kind>;
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class sext_ter_rmw_8_64<PatFrag kind> :
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PatFrag<(ops node:$addr, node:$exp, node:$new),
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(anyext (i32 (assertzext (i32
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(kind node:$addr,
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(i32 (trunc (i64 node:$exp))),
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(i32 (trunc (i64 node:$new))))))))>;
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class sext_ter_rmw_16_64<PatFrag kind> : sext_ter_rmw_8_64<kind>;
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// 32->64 sext RMW gets selected as i32.atomic.rmw.***, i64.extend_i32_s
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defm : TerRMWPat<i32, zext_ter_rmw_8_32<atomic_cmp_swap_8>, "ATOMIC_RMW8_U_CMPXCHG_I32">;
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defm : TerRMWPat<i32, zext_ter_rmw_16_32<atomic_cmp_swap_16>, "ATOMIC_RMW16_U_CMPXCHG_I32">;
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defm : TerRMWPat<i64, zext_ter_rmw_8_64<atomic_cmp_swap_8>, "ATOMIC_RMW8_U_CMPXCHG_I64">;
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defm : TerRMWPat<i64, zext_ter_rmw_16_64<atomic_cmp_swap_16>, "ATOMIC_RMW16_U_CMPXCHG_I64">;
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defm : TerRMWPat<i64, zext_ter_rmw_32_64<atomic_cmp_swap_32>, "ATOMIC_RMW32_U_CMPXCHG_I64">;
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defm : TerRMWPat<i32, sext_ter_rmw_8_32<atomic_cmp_swap_8>, "ATOMIC_RMW8_U_CMPXCHG_I32">;
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defm : TerRMWPat<i32, sext_ter_rmw_16_32<atomic_cmp_swap_16>, "ATOMIC_RMW16_U_CMPXCHG_I32">;
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defm : TerRMWPat<i64, sext_ter_rmw_8_64<atomic_cmp_swap_8>, "ATOMIC_RMW8_U_CMPXCHG_I64">;
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||
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defm : TerRMWPat<i64, sext_ter_rmw_16_64<atomic_cmp_swap_16>, "ATOMIC_RMW16_U_CMPXCHG_I64">;
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