100 lines
2.8 KiB
C++
100 lines
2.8 KiB
C++
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//===-- RISCVTargetParser.cpp - Parser for target features ------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements a target parser to recognise hardware features
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// for RISC-V CPUs.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/TargetParser/RISCVTargetParser.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/StringSwitch.h"
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#include "llvm/TargetParser/Triple.h"
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namespace llvm {
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namespace RISCV {
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enum CPUKind : unsigned {
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#define PROC(ENUM, NAME, DEFAULT_MARCH, FAST_UNALIGN) CK_##ENUM,
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#define TUNE_PROC(ENUM, NAME) CK_##ENUM,
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#include "llvm/TargetParser/RISCVTargetParserDef.inc"
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};
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struct CPUInfo {
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StringLiteral Name;
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StringLiteral DefaultMarch;
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bool FastUnalignedAccess;
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bool is64Bit() const { return DefaultMarch.starts_with("rv64"); }
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};
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constexpr CPUInfo RISCVCPUInfo[] = {
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#define PROC(ENUM, NAME, DEFAULT_MARCH, FAST_UNALIGN) \
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{NAME, DEFAULT_MARCH, FAST_UNALIGN},
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#include "llvm/TargetParser/RISCVTargetParserDef.inc"
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};
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static const CPUInfo *getCPUInfoByName(StringRef CPU) {
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for (auto &C : RISCVCPUInfo)
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if (C.Name == CPU)
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return &C;
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return nullptr;
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}
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bool hasFastUnalignedAccess(StringRef CPU) {
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const CPUInfo *Info = getCPUInfoByName(CPU);
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return Info && Info->FastUnalignedAccess;
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}
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bool parseCPU(StringRef CPU, bool IsRV64) {
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const CPUInfo *Info = getCPUInfoByName(CPU);
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if (!Info)
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return false;
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return Info->is64Bit() == IsRV64;
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}
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bool parseTuneCPU(StringRef TuneCPU, bool IsRV64) {
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std::optional<CPUKind> Kind =
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llvm::StringSwitch<std::optional<CPUKind>>(TuneCPU)
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#define TUNE_PROC(ENUM, NAME) .Case(NAME, CK_##ENUM)
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#include "llvm/TargetParser/RISCVTargetParserDef.inc"
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.Default(std::nullopt);
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if (Kind.has_value())
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return true;
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// Fallback to parsing as a CPU.
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return parseCPU(TuneCPU, IsRV64);
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}
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StringRef getMArchFromMcpu(StringRef CPU) {
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const CPUInfo *Info = getCPUInfoByName(CPU);
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if (!Info)
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return "";
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return Info->DefaultMarch;
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}
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void fillValidCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64) {
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for (const auto &C : RISCVCPUInfo) {
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if (IsRV64 == C.is64Bit())
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Values.emplace_back(C.Name);
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}
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}
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void fillValidTuneCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64) {
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for (const auto &C : RISCVCPUInfo) {
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if (IsRV64 == C.is64Bit())
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Values.emplace_back(C.Name);
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}
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#define TUNE_PROC(ENUM, NAME) Values.emplace_back(StringRef(NAME));
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#include "llvm/TargetParser/RISCVTargetParserDef.inc"
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}
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} // namespace RISCV
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} // namespace llvm
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