94 lines
3.7 KiB
LLVM
94 lines
3.7 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
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; RUN: opt -passes='loop(loop-deletion),loop-mssa(loop-predication,licm<allowspeculation>,simple-loop-unswitch<nontrivial>),loop(loop-predication)' -S < %s | FileCheck %s
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target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128-ni:1-p2:32:8:8:32-ni:2"
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target triple = "x86_64-unknown-linux-gnu"
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define void @test(i32 %arg) {
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; CHECK-LABEL: define void @test
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; CHECK-SAME: (i32 [[ARG:%.*]]) {
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; CHECK-NEXT: bb:
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; CHECK-NEXT: br label [[BB1:%.*]]
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; CHECK: bb1:
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; CHECK-NEXT: br label [[BB2:%.*]]
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; CHECK: bb2:
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; CHECK-NEXT: br i1 false, label [[BB3_PREHEADER:%.*]], label [[BB1]]
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; CHECK: bb3.preheader:
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; CHECK-NEXT: [[LOAD_LE:%.*]] = load i32, ptr null, align 4
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; CHECK-NEXT: br label [[BB3:%.*]]
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; CHECK: bb3.loopexit:
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; CHECK-NEXT: br label [[BB3]]
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; CHECK: bb3:
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; CHECK-NEXT: [[PHI:%.*]] = phi i32 [ [[ADD:%.*]], [[BB3_LOOPEXIT:%.*]] ], [ 0, [[BB3_PREHEADER]] ]
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; CHECK-NEXT: [[ADD]] = add i32 [[PHI]], 1
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; CHECK-NEXT: [[ICMP:%.*]] = icmp ult i32 [[PHI]], [[LOAD_LE]]
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; CHECK-NEXT: br i1 [[ICMP]], label [[BB5:%.*]], label [[BB4:%.*]]
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; CHECK: bb4:
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; CHECK-NEXT: ret void
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; CHECK: bb5:
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; CHECK-NEXT: [[CALL:%.*]] = call i1 @llvm.experimental.widenable.condition()
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; CHECK-NEXT: br i1 [[CALL]], label [[BB9_PREHEADER:%.*]], label [[BB14:%.*]]
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; CHECK: bb9.preheader:
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; CHECK-NEXT: br label [[BB9:%.*]]
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; CHECK: bb6:
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; CHECK-NEXT: [[ADD7:%.*]] = add i32 [[PHI10:%.*]], 1
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; CHECK-NEXT: [[ICMP8:%.*]] = icmp ugt i32 [[PHI10]], 1
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; CHECK-NEXT: br i1 [[ICMP8]], label [[BB3_LOOPEXIT]], label [[BB9]]
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; CHECK: bb9:
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; CHECK-NEXT: [[PHI10]] = phi i32 [ [[ADD7]], [[BB6:%.*]] ], [ [[PHI]], [[BB9_PREHEADER]] ]
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; CHECK-NEXT: [[ICMP11:%.*]] = icmp ult i32 [[PHI10]], [[ARG]]
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; CHECK-NEXT: [[CALL12:%.*]] = call i1 @llvm.experimental.widenable.condition()
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; CHECK-NEXT: [[AND:%.*]] = and i1 [[ICMP11]], true
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; CHECK-NEXT: br i1 [[AND]], label [[BB6]], label [[BB13:%.*]]
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; CHECK: bb13:
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; CHECK-NEXT: ret void
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; CHECK: bb14:
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; CHECK-NEXT: ret void
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;
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bb:
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br label %bb1
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bb1: ; preds = %bb2, %bb
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%load = load i32, ptr null, align 4
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br label %bb2
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bb2: ; preds = %bb1
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br i1 false, label %bb3, label %bb1
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bb3: ; preds = %bb6, %bb2
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%phi = phi i32 [ %add, %bb6 ], [ 0, %bb2 ]
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%add = add i32 %phi, 1
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%icmp = icmp ult i32 %phi, %load
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br i1 %icmp, label %bb5, label %bb4
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bb4: ; preds = %bb3
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ret void
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bb5: ; preds = %bb3
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%call = call i1 @llvm.experimental.widenable.condition()
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br i1 %call, label %bb9, label %bb14
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bb6: ; preds = %bb9
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%add7 = add i32 %phi10, 1
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%icmp8 = icmp ugt i32 %phi10, 1
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br i1 %icmp8, label %bb3, label %bb9
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bb9: ; preds = %bb6, %bb5
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%phi10 = phi i32 [ %add7, %bb6 ], [ %phi, %bb5 ]
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%icmp11 = icmp ult i32 %phi10, %arg
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%call12 = call i1 @llvm.experimental.widenable.condition()
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%and = and i1 %icmp11, %call12
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br i1 %and, label %bb6, label %bb13
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bb13: ; preds = %bb9
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ret void
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bb14: ; preds = %bb5
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ret void
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}
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; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(inaccessiblemem: readwrite)
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declare noundef i1 @llvm.experimental.widenable.condition() #0
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attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(inaccessiblemem: readwrite) }
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