158 lines
4.7 KiB
Text
158 lines
4.7 KiB
Text
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple aarch64 -run-pass=aarch64-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
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# Check that we can fold a G_SEXT_INREG fed by a G_ASHR/G_LSHR into a G_SBFX.
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...
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---
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name: sextinreg_ashr_to_sbfx
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tracksRegLiveness: true
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legalized: true
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body: |
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bb.0:
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liveins: $w0
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; CHECK-LABEL: name: sextinreg_ashr_to_sbfx
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; CHECK: liveins: $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %x:_(s32) = COPY $w0
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; CHECK-NEXT: %lsb:_(s32) = G_CONSTANT i32 5
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
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; CHECK-NEXT: %sext_inreg:_(s32) = G_SBFX %x, %lsb(s32), [[C]]
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; CHECK-NEXT: $w0 = COPY %sext_inreg(s32)
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%x:_(s32) = COPY $w0
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%lsb:_(s32) = G_CONSTANT i32 5
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%shift:_(s32) = G_ASHR %x, %lsb
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%sext_inreg:_(s32) = G_SEXT_INREG %shift, 10
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$w0 = COPY %sext_inreg
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RET_ReallyLR implicit $w0
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...
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---
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name: sextinreg_lshr_to_sbfx
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tracksRegLiveness: true
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legalized: true
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body: |
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bb.0:
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liveins: $w0
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; CHECK-LABEL: name: sextinreg_lshr_to_sbfx
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; CHECK: liveins: $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %x:_(s32) = COPY $w0
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; CHECK-NEXT: %lsb:_(s32) = G_CONSTANT i32 5
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
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; CHECK-NEXT: %sext_inreg:_(s32) = G_SBFX %x, %lsb(s32), [[C]]
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; CHECK-NEXT: $w0 = COPY %sext_inreg(s32)
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%x:_(s32) = COPY $w0
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%lsb:_(s32) = G_CONSTANT i32 5
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%shift:_(s32) = G_LSHR %x, %lsb
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%sext_inreg:_(s32) = G_SEXT_INREG %shift, 10
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$w0 = COPY %sext_inreg
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RET_ReallyLR implicit $w0
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...
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---
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name: dont_apply_no_constant
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tracksRegLiveness: true
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legalized: true
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body: |
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bb.0:
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liveins: $w0
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; AArch64 needs a constant on the shift for this combine.
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; CHECK-LABEL: name: dont_apply_no_constant
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; CHECK: liveins: $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %x:_(s32) = COPY $w0
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; CHECK-NEXT: %y:_(s32) = COPY $w0
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; CHECK-NEXT: %shift:_(s32) = G_LSHR %x, %y(s32)
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; CHECK-NEXT: %sext_inreg:_(s32) = G_SEXT_INREG %shift, 10
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; CHECK-NEXT: $w0 = COPY %sext_inreg(s32)
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%x:_(s32) = COPY $w0
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%y:_(s32) = COPY $w0
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%shift:_(s32) = G_LSHR %x, %y
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%sext_inreg:_(s32) = G_SEXT_INREG %shift, 10
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$w0 = COPY %sext_inreg
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RET_ReallyLR implicit $w0
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...
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---
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name: dont_apply_shift_imm_too_large
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tracksRegLiveness: true
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legalized: true
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body: |
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bb.0:
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liveins: $w0
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; LSB must be in 0-31.
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; CHECK-LABEL: name: dont_apply_shift_imm_too_large
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; CHECK: liveins: $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %x:_(s32) = COPY $w0
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; CHECK-NEXT: %lsb:_(s32) = G_CONSTANT i32 32
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; CHECK-NEXT: %shift:_(s32) = G_ASHR %x, %lsb(s32)
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; CHECK-NEXT: $w0 = COPY %shift(s32)
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%x:_(s32) = COPY $w0
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%lsb:_(s32) = G_CONSTANT i32 32
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%shift:_(s32) = G_ASHR %x, %lsb
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%sext_inreg:_(s32) = G_SEXT_INREG %shift, 1
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$w0 = COPY %sext_inreg
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RET_ReallyLR implicit $w0
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...
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---
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name: dont_apply_negative_shift_imm
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tracksRegLiveness: true
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legalized: true
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body: |
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bb.0:
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liveins: $w0
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; LSB must be in 0-31.
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; CHECK-LABEL: name: dont_apply_negative_shift_imm
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; CHECK: liveins: $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %x:_(s32) = COPY $w0
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; CHECK-NEXT: %lsb:_(s32) = G_CONSTANT i32 -1
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; CHECK-NEXT: %shift:_(s32) = G_ASHR %x, %lsb(s32)
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; CHECK-NEXT: $w0 = COPY %shift(s32)
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%x:_(s32) = COPY $w0
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%lsb:_(s32) = G_CONSTANT i32 -1
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%shift:_(s32) = G_ASHR %x, %lsb
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%sext_inreg:_(s32) = G_SEXT_INREG %shift, 1
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$w0 = COPY %sext_inreg
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RET_ReallyLR implicit $w0
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...
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---
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name: dont_apply_more_than_one_use
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tracksRegLiveness: true
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legalized: true
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body: |
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bb.0:
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liveins: $w0
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; CHECK-LABEL: name: dont_apply_more_than_one_use
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; CHECK: liveins: $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %x:_(s32) = COPY $w0
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; CHECK-NEXT: %lsb:_(s32) = G_CONSTANT i32 1
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; CHECK-NEXT: %shift:_(s32) = G_ASHR %x, %lsb(s32)
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; CHECK-NEXT: %sext_inreg:_(s32) = G_SEXT_INREG %shift, 1
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; CHECK-NEXT: %mul:_(s32) = G_MUL %shift, %sext_inreg
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; CHECK-NEXT: $w0 = COPY %mul(s32)
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%x:_(s32) = COPY $w0
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%lsb:_(s32) = G_CONSTANT i32 1
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%shift:_(s32) = G_ASHR %x, %lsb
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%sext_inreg:_(s32) = G_SEXT_INREG %shift, 1
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%mul:_(s32) = G_MUL %shift, %sext_inreg
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$w0 = COPY %mul
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RET_ReallyLR implicit $w0
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