222 lines
6.3 KiB
Text
222 lines
6.3 KiB
Text
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN:llc %s -verify-machineinstrs -mtriple=aarch64-unknown-unknown -run-pass=legalizer -global-isel-abort=1 -o - | FileCheck %s
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---
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name: smin_s32
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alignment: 4
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tracksRegLiveness: true
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liveins:
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- { reg: '$w0' }
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- { reg: '$w1' }
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body: |
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bb.1:
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liveins: $w0, $w1
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; CHECK-LABEL: name: smin_s32
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; CHECK: liveins: $w0, $w1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
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; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY]](s32), [[COPY1]]
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; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]]
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; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%0:_(s32) = COPY $w0
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%1:_(s32) = COPY $w1
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%2:_(s32) = G_SMIN %0, %1
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$w0 = COPY %2(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: smin_s64
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alignment: 4
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tracksRegLiveness: true
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liveins:
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- { reg: '$x0' }
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- { reg: '$x1' }
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body: |
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bb.1:
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liveins: $x0, $x1
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; CHECK-LABEL: name: smin_s64
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; CHECK: liveins: $x0, $x1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
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; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY]](s64), [[COPY1]]
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; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]]
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; CHECK-NEXT: $x0 = COPY [[SELECT]](s64)
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; CHECK-NEXT: RET_ReallyLR implicit $x0
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%0:_(s64) = COPY $x0
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%1:_(s64) = COPY $x1
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%2:_(s64) = G_SMIN %0, %1
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$x0 = COPY %2(s64)
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RET_ReallyLR implicit $x0
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...
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---
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name: smax_s32
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alignment: 4
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tracksRegLiveness: true
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liveins:
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- { reg: '$w0' }
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- { reg: '$w1' }
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body: |
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bb.1:
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liveins: $w0, $w1
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; CHECK-LABEL: name: smax_s32
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; CHECK: liveins: $w0, $w1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
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; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[COPY]](s32), [[COPY1]]
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; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]]
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; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%0:_(s32) = COPY $w0
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%1:_(s32) = COPY $w1
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%2:_(s32) = G_SMAX %0, %1
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$w0 = COPY %2(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: smax_s64
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alignment: 4
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tracksRegLiveness: true
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liveins:
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- { reg: '$x0' }
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- { reg: '$x1' }
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body: |
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bb.1:
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liveins: $x0, $x1
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; CHECK-LABEL: name: smax_s64
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; CHECK: liveins: $x0, $x1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
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; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[COPY]](s64), [[COPY1]]
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; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]]
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; CHECK-NEXT: $x0 = COPY [[SELECT]](s64)
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; CHECK-NEXT: RET_ReallyLR implicit $x0
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%0:_(s64) = COPY $x0
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%1:_(s64) = COPY $x1
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%2:_(s64) = G_SMAX %0, %1
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$x0 = COPY %2(s64)
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RET_ReallyLR implicit $x0
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...
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---
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name: umin_s32
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alignment: 4
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tracksRegLiveness: true
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liveins:
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- { reg: '$w0' }
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- { reg: '$w1' }
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body: |
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bb.1:
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liveins: $w0, $w1
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; CHECK-LABEL: name: umin_s32
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; CHECK: liveins: $w0, $w1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
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; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY1]]
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; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]]
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; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%0:_(s32) = COPY $w0
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%1:_(s32) = COPY $w1
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%2:_(s32) = G_UMIN %0, %1
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$w0 = COPY %2(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: umin_s64
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alignment: 4
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tracksRegLiveness: true
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liveins:
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- { reg: '$x0' }
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- { reg: '$x1' }
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body: |
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bb.1:
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liveins: $x0, $x1
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; CHECK-LABEL: name: umin_s64
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; CHECK: liveins: $x0, $x1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
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; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s64), [[COPY1]]
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; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]]
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; CHECK-NEXT: $x0 = COPY [[SELECT]](s64)
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; CHECK-NEXT: RET_ReallyLR implicit $x0
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%0:_(s64) = COPY $x0
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%1:_(s64) = COPY $x1
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%2:_(s64) = G_UMIN %0, %1
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$x0 = COPY %2(s64)
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RET_ReallyLR implicit $x0
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...
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---
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name: umax_s32
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alignment: 4
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tracksRegLiveness: true
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liveins:
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- { reg: '$w0' }
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- { reg: '$w1' }
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body: |
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bb.1:
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liveins: $w0, $w1
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; CHECK-LABEL: name: umax_s32
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; CHECK: liveins: $w0, $w1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
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; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY1]]
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; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]]
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; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%0:_(s32) = COPY $w0
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%1:_(s32) = COPY $w1
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%2:_(s32) = G_UMAX %0, %1
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$w0 = COPY %2(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: umax_s64
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alignment: 4
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tracksRegLiveness: true
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liveins:
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- { reg: '$x0' }
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- { reg: '$x1' }
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body: |
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bb.1:
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liveins: $x0, $x1
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; CHECK-LABEL: name: umax_s64
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; CHECK: liveins: $x0, $x1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
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; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s64), [[COPY1]]
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; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]]
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; CHECK-NEXT: $x0 = COPY [[SELECT]](s64)
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; CHECK-NEXT: RET_ReallyLR implicit $x0
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%0:_(s64) = COPY $x0
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%1:_(s64) = COPY $x1
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%2:_(s64) = G_UMAX %0, %1
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$x0 = COPY %2(s64)
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RET_ReallyLR implicit $x0
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...
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