bolt/deps/llvm-18.1.8/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-binop-reassoc.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s

# Combins: (Opc (Opc X, C1), C2) -> (Opc X, (Opc C1, C2))
---
name:            test1_add_move_inner_cst_to_fold
alignment:       4
tracksRegLiveness: true
liveins:
  - { reg: '$x0' }
body:             |
  bb.1:
    liveins: $x0

    ; CHECK-LABEL: name: test1_add_move_inner_cst_to_fold
    ; CHECK: liveins: $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %x:_(s64) = COPY $x0
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 88
    ; CHECK-NEXT: %add_outer:_(s64) = G_ADD %x, [[C]]
    ; CHECK-NEXT: $x0 = COPY %add_outer(s64)
    ; CHECK-NEXT: RET_ReallyLR implicit $x0
    %x:_(s64) = COPY $x0
    %C1:_(s64) = G_CONSTANT i64 64
    %C2:_(s64) = G_CONSTANT i64 24
    %add_inner:_(s64) = G_ADD %x, %C1
    %add_outer:_(s64) = G_ADD %add_inner, %C2
    $x0 = COPY %add_outer
    RET_ReallyLR implicit $x0

...

# (op (op x, c1), y) -> (op (op x, y), c1)
---
name:            test2_add_move_inner_cst_to_rhs
alignment:       4
tracksRegLiveness: true
liveins:
  - { reg: '$x0' }
body:             |
  bb.1:
    liveins: $x0, $x1

    ; CHECK-LABEL: name: test2_add_move_inner_cst_to_rhs
    ; CHECK: liveins: $x0, $x1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %x:_(s64) = COPY $x0
    ; CHECK-NEXT: %C1:_(s64) = G_CONSTANT i64 64
    ; CHECK-NEXT: %y:_(s64) = COPY $x1
    ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD %x, %y
    ; CHECK-NEXT: %add_outer:_(s64) = G_ADD [[ADD]], %C1
    ; CHECK-NEXT: $x0 = COPY %add_outer(s64)
    ; CHECK-NEXT: RET_ReallyLR implicit $x0
    %x:_(s64) = COPY $x0
    %C1:_(s64) = G_CONSTANT i64 64
    %y:_(s64) = COPY $x1
    %add_inner:_(s64) = G_ADD %x, %C1
    %add_outer:_(s64) = G_ADD %add_inner, %y
    $x0 = COPY %add_outer
    RET_ReallyLR implicit $x0

...
---
name:            test2_add_move_inner_cst_to_rhs_multiuse
alignment:       4
tracksRegLiveness: true
liveins:
  - { reg: '$x0' }
body:             |
  bb.1:
    liveins: $x0, $x1

    ; CHECK-LABEL: name: test2_add_move_inner_cst_to_rhs_multiuse
    ; CHECK: liveins: $x0, $x1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %x:_(s64) = COPY $x0
    ; CHECK-NEXT: %C1:_(s64) = G_CONSTANT i64 64
    ; CHECK-NEXT: %y:_(s64) = COPY $x1
    ; CHECK-NEXT: %add_inner:_(s64) = G_ADD %x, %C1
    ; CHECK-NEXT: %add_outer:_(s64) = G_ADD %add_inner, %y
    ; CHECK-NEXT: $x0 = COPY %add_outer(s64)
    ; CHECK-NEXT: $x1 = COPY %add_inner(s64)
    ; CHECK-NEXT: RET_ReallyLR implicit $x0
    %x:_(s64) = COPY $x0
    %C1:_(s64) = G_CONSTANT i64 64
    %y:_(s64) = COPY $x1
    %add_inner:_(s64) = G_ADD %x, %C1
    %add_outer:_(s64) = G_ADD %add_inner, %y
    $x0 = COPY %add_outer
    $x1 = COPY %add_inner
    RET_ReallyLR implicit $x0

...
---
name:            test2_add_move_inner_cst_to_rhs_vector
alignment:       4
tracksRegLiveness: true
liveins:
  - { reg: '$x0' }
body:             |
  bb.1:
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test2_add_move_inner_cst_to_rhs_vector
    ; CHECK: liveins: $q0, $q1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %x:_(<2 x s64>) = COPY $q0
    ; CHECK-NEXT: %C1:_(s64) = G_CONSTANT i64 64
    ; CHECK-NEXT: %VEC_C1:_(<2 x s64>) = G_BUILD_VECTOR %C1(s64), %C1(s64)
    ; CHECK-NEXT: %y:_(<2 x s64>) = COPY $q1
    ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD %x, %y
    ; CHECK-NEXT: %add_outer:_(<2 x s64>) = G_ADD [[ADD]], %VEC_C1
    ; CHECK-NEXT: $q0 = COPY %add_outer(<2 x s64>)
    ; CHECK-NEXT: RET_ReallyLR implicit $q0
    %x:_(<2 x s64>) = COPY $q0
    %C1:_(s64) = G_CONSTANT i64 64
    %VEC_C1:_(<2 x s64>) = G_BUILD_VECTOR %C1, %C1
    %y:_(<2 x s64>) = COPY $q1
    %add_inner:_(<2 x s64>) = G_ADD %x, %VEC_C1
    %add_outer:_(<2 x s64>) = G_ADD %add_inner, %y
    $q0 = COPY %add_outer
    RET_ReallyLR implicit $q0

...