181 lines
5 KiB
Text
181 lines
5 KiB
Text
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple aarch64 -debugify-and-strip-all-safe -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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# Check that we remove hints during selection.
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...
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---
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name: assert_zext_gpr
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $w0, $w1
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; CHECK-LABEL: name: assert_zext_gpr
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; CHECK: liveins: $w0, $w1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %copy:gpr32 = COPY $w0
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; CHECK-NEXT: $w1 = COPY %copy
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; CHECK-NEXT: RET_ReallyLR implicit $w1
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%copy:gpr(s32) = COPY $w0
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%copy_assert_zext:gpr(s32) = G_ASSERT_ZEXT %copy, 16
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$w1 = COPY %copy_assert_zext(s32)
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RET_ReallyLR implicit $w1
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...
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---
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name: assert_zext_fpr
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $s0, $s1
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; CHECK-LABEL: name: assert_zext_fpr
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; CHECK: liveins: $s0, $s1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %copy:fpr32 = COPY $s0
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; CHECK-NEXT: $s1 = COPY %copy
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; CHECK-NEXT: RET_ReallyLR implicit $s1
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%copy:fpr(s32) = COPY $s0
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%copy_assert_zext:fpr(s32) = G_ASSERT_ZEXT %copy, 16
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$s1 = COPY %copy_assert_zext(s32)
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RET_ReallyLR implicit $s1
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...
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---
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name: assert_zext_in_between_cross_bank
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $s0, $w1
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; CHECK-LABEL: name: assert_zext_in_between_cross_bank
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; CHECK: liveins: $s0, $w1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %copy:fpr32 = COPY $s0
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; CHECK-NEXT: $w1 = COPY %copy
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; CHECK-NEXT: RET_ReallyLR implicit $w1
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%copy:fpr(s32) = COPY $s0
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%copy_assert_zext:fpr(s32) = G_ASSERT_ZEXT %copy, 16
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$w1 = COPY %copy_assert_zext(s32)
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RET_ReallyLR implicit $w1
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...
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---
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name: assert_zext_decided_dst_class
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $w0, $w1, $w2
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; Users of G_ASSERT_ZEXT may end up deciding the destination register class.
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; Make sure that the source register class is constrained.
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; CHECK-LABEL: name: assert_zext_decided_dst_class
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; CHECK: liveins: $w0, $w1, $w2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %copy_with_rc:gpr32sp = COPY $w2
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; CHECK-NEXT: $w1 = COPY %copy_with_rc
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; CHECK-NEXT: RET_ReallyLR implicit $w1
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%copy:gpr(s32) = COPY $w0
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%copy_assert_zext:gpr(s32) = G_ASSERT_ZEXT %copy, 16
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%copy_with_rc:gpr32sp(s32) = COPY $w2
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$w1 = COPY %copy_with_rc(s32)
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RET_ReallyLR implicit $w1
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...
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---
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name: assert_sext_gpr
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $w0, $w1
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; CHECK-LABEL: name: assert_sext_gpr
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; CHECK: liveins: $w0, $w1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %copy:gpr32 = COPY $w0
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; CHECK-NEXT: $w1 = COPY %copy
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; CHECK-NEXT: RET_ReallyLR implicit $w1
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%copy:gpr(s32) = COPY $w0
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%copy_assert_sext:gpr(s32) = G_ASSERT_SEXT %copy, 16
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$w1 = COPY %copy_assert_sext(s32)
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RET_ReallyLR implicit $w1
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...
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---
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name: assert_sext_fpr
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $s0, $s1
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; CHECK-LABEL: name: assert_sext_fpr
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; CHECK: liveins: $s0, $s1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %copy:fpr32 = COPY $s0
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; CHECK-NEXT: $s1 = COPY %copy
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; CHECK-NEXT: RET_ReallyLR implicit $s1
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%copy:fpr(s32) = COPY $s0
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%copy_assert_sext:fpr(s32) = G_ASSERT_SEXT %copy, 16
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$s1 = COPY %copy_assert_sext(s32)
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RET_ReallyLR implicit $s1
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...
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---
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name: assert_sext_in_between_cross_bank
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $s0, $w1
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; CHECK-LABEL: name: assert_sext_in_between_cross_bank
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; CHECK: liveins: $s0, $w1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %copy:fpr32 = COPY $s0
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; CHECK-NEXT: $w1 = COPY %copy
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; CHECK-NEXT: RET_ReallyLR implicit $w1
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%copy:fpr(s32) = COPY $s0
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%copy_assert_sext:fpr(s32) = G_ASSERT_SEXT %copy, 16
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$w1 = COPY %copy_assert_sext(s32)
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RET_ReallyLR implicit $w1
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...
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---
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name: assert_sext_decided_dst_class
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $w0, $w1, $w2
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; Users of G_ASSERT_SEXT may end up deciding the destination register class.
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; Make sure that the source register class is constrained.
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; CHECK-LABEL: name: assert_sext_decided_dst_class
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; CHECK: liveins: $w0, $w1, $w2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %copy_with_rc:gpr32sp = COPY $w2
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; CHECK-NEXT: $w1 = COPY %copy_with_rc
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; CHECK-NEXT: RET_ReallyLR implicit $w1
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%copy:gpr(s32) = COPY $w0
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%copy_assert_sext:gpr(s32) = G_ASSERT_SEXT %copy, 16
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%copy_with_rc:gpr32sp(s32) = COPY $w2
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$w1 = COPY %copy_with_rc(s32)
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RET_ReallyLR implicit $w1
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