219 lines
7.4 KiB
Text
219 lines
7.4 KiB
Text
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O0 -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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---
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name: mul_i64_sext_imm32
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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- { id: 3, class: gpr }
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body: |
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bb.0:
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liveins: $w0
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; Make sure InstructionSelector is able to match a pattern
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; with an SDNodeXForm, trunc_imm.
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; def : Pat<(i64 (mul (sext GPR32:$Rn), (s64imm_32bit:$C))),
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; (SMADDLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), XZR)>;
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; CHECK-LABEL: name: mul_i64_sext_imm32
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
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; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 3
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; CHECK-NEXT: [[SMADDLrrr:%[0-9]+]]:gpr64 = SMADDLrrr [[COPY]], [[MOVi32imm]], $xzr
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; CHECK-NEXT: $x0 = COPY [[SMADDLrrr]]
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%0:gpr(s32) = COPY $w0
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%1:gpr(s64) = G_SEXT %0(s32)
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%2:gpr(s64) = G_CONSTANT i64 3
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%3:gpr(s64) = G_MUL %1, %2
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$x0 = COPY %3(s64)
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...
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---
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name: umulh_v8s16
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legalized: true
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regBankSelected: true
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exposesReturnsTwice: false
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tracksRegLiveness: true
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liveins:
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- { reg: '$q0', virtual-reg: '' }
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body: |
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bb.1:
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liveins: $q0, $q1
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; CHECK-LABEL: name: umulh_v8s16
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; CHECK: liveins: $q0, $q1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
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; CHECK-NEXT: [[UMULLv8i16_v4i32_:%[0-9]+]]:fpr128 = UMULLv8i16_v4i32 [[COPY]], [[COPY1]]
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[COPY1]].dsub
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr64 = COPY [[COPY]].dsub
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; CHECK-NEXT: [[UMULLv4i16_v4i32_:%[0-9]+]]:fpr128 = UMULLv4i16_v4i32 [[COPY3]], [[COPY2]]
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; CHECK-NEXT: %mul:fpr128 = UZP2v8i16 [[UMULLv4i16_v4i32_]], [[UMULLv8i16_v4i32_]]
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; CHECK-NEXT: $q0 = COPY %mul
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; CHECK-NEXT: RET_ReallyLR implicit $q0
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%0:fpr(<8 x s16>) = COPY $q0
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%1:fpr(<8 x s16>) = COPY $q1
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%mul:fpr(<8 x s16>) = G_UMULH %0, %1
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$q0 = COPY %mul(<8 x s16>)
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RET_ReallyLR implicit $q0
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...
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---
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name: umulh_v16s8
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legalized: true
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regBankSelected: true
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exposesReturnsTwice: false
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tracksRegLiveness: true
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liveins:
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- { reg: '$q0', virtual-reg: '' }
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body: |
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bb.1:
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liveins: $q0, $q1
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; CHECK-LABEL: name: umulh_v16s8
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; CHECK: liveins: $q0, $q1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
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; CHECK-NEXT: [[UMULLv16i8_v8i16_:%[0-9]+]]:fpr128 = UMULLv16i8_v8i16 [[COPY]], [[COPY1]]
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[COPY1]].dsub
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr64 = COPY [[COPY]].dsub
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; CHECK-NEXT: [[UMULLv8i8_v8i16_:%[0-9]+]]:fpr128 = UMULLv8i8_v8i16 [[COPY3]], [[COPY2]]
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; CHECK-NEXT: %mul:fpr128 = UZP2v16i8 [[UMULLv8i8_v8i16_]], [[UMULLv16i8_v8i16_]]
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; CHECK-NEXT: $q0 = COPY %mul
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; CHECK-NEXT: RET_ReallyLR implicit $q0
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%0:fpr(<16 x s8>) = COPY $q0
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%1:fpr(<16 x s8>) = COPY $q1
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%mul:fpr(<16 x s8>) = G_UMULH %0, %1
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$q0 = COPY %mul(<16 x s8>)
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RET_ReallyLR implicit $q0
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...
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---
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name: umulh_v4s32
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legalized: true
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regBankSelected: true
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exposesReturnsTwice: false
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tracksRegLiveness: true
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liveins:
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- { reg: '$q0', virtual-reg: '' }
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body: |
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bb.1:
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liveins: $q0, $q1
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; CHECK-LABEL: name: umulh_v4s32
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; CHECK: liveins: $q0, $q1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
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; CHECK-NEXT: [[UMULLv4i32_v2i64_:%[0-9]+]]:fpr128 = UMULLv4i32_v2i64 [[COPY]], [[COPY1]]
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[COPY1]].dsub
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr64 = COPY [[COPY]].dsub
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; CHECK-NEXT: [[UMULLv2i32_v2i64_:%[0-9]+]]:fpr128 = UMULLv2i32_v2i64 [[COPY3]], [[COPY2]]
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; CHECK-NEXT: %mul:fpr128 = UZP2v4i32 [[UMULLv2i32_v2i64_]], [[UMULLv4i32_v2i64_]]
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; CHECK-NEXT: $q0 = COPY %mul
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; CHECK-NEXT: RET_ReallyLR implicit $q0
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%0:fpr(<4 x s32>) = COPY $q0
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%1:fpr(<4 x s32>) = COPY $q1
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%mul:fpr(<4 x s32>) = G_UMULH %0, %1
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$q0 = COPY %mul(<4 x s32>)
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RET_ReallyLR implicit $q0
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...
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---
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name: smulh_v8s16
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legalized: true
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regBankSelected: true
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exposesReturnsTwice: false
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tracksRegLiveness: true
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liveins:
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- { reg: '$q0', virtual-reg: '' }
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body: |
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bb.1:
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liveins: $q0, $q1
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; CHECK-LABEL: name: smulh_v8s16
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; CHECK: liveins: $q0, $q1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
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; CHECK-NEXT: [[SMULLv8i16_v4i32_:%[0-9]+]]:fpr128 = SMULLv8i16_v4i32 [[COPY]], [[COPY1]]
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[COPY1]].dsub
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr64 = COPY [[COPY]].dsub
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; CHECK-NEXT: [[SMULLv4i16_v4i32_:%[0-9]+]]:fpr128 = SMULLv4i16_v4i32 [[COPY3]], [[COPY2]]
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; CHECK-NEXT: %mul:fpr128 = UZP2v8i16 [[SMULLv4i16_v4i32_]], [[SMULLv8i16_v4i32_]]
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; CHECK-NEXT: $q0 = COPY %mul
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; CHECK-NEXT: RET_ReallyLR implicit $q0
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%0:fpr(<8 x s16>) = COPY $q0
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%1:fpr(<8 x s16>) = COPY $q1
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%mul:fpr(<8 x s16>) = G_SMULH %0, %1
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$q0 = COPY %mul(<8 x s16>)
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RET_ReallyLR implicit $q0
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...
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---
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name: smulh_v16s8
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legalized: true
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regBankSelected: true
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exposesReturnsTwice: false
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tracksRegLiveness: true
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liveins:
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- { reg: '$q0', virtual-reg: '' }
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body: |
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bb.1:
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liveins: $q0, $q1
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; CHECK-LABEL: name: smulh_v16s8
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; CHECK: liveins: $q0, $q1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
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; CHECK-NEXT: [[SMULLv16i8_v8i16_:%[0-9]+]]:fpr128 = SMULLv16i8_v8i16 [[COPY]], [[COPY1]]
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[COPY1]].dsub
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr64 = COPY [[COPY]].dsub
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; CHECK-NEXT: [[SMULLv8i8_v8i16_:%[0-9]+]]:fpr128 = SMULLv8i8_v8i16 [[COPY3]], [[COPY2]]
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; CHECK-NEXT: %mul:fpr128 = UZP2v16i8 [[SMULLv8i8_v8i16_]], [[SMULLv16i8_v8i16_]]
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; CHECK-NEXT: $q0 = COPY %mul
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; CHECK-NEXT: RET_ReallyLR implicit $q0
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%0:fpr(<16 x s8>) = COPY $q0
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%1:fpr(<16 x s8>) = COPY $q1
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%mul:fpr(<16 x s8>) = G_SMULH %0, %1
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$q0 = COPY %mul(<16 x s8>)
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RET_ReallyLR implicit $q0
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...
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---
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name: smulh_v4s32
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legalized: true
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regBankSelected: true
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exposesReturnsTwice: false
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tracksRegLiveness: true
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liveins:
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- { reg: '$q0', virtual-reg: '' }
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body: |
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bb.1:
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liveins: $q0, $q1
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; CHECK-LABEL: name: smulh_v4s32
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; CHECK: liveins: $q0, $q1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
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; CHECK-NEXT: [[SMULLv4i32_v2i64_:%[0-9]+]]:fpr128 = SMULLv4i32_v2i64 [[COPY]], [[COPY1]]
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[COPY1]].dsub
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr64 = COPY [[COPY]].dsub
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; CHECK-NEXT: [[SMULLv2i32_v2i64_:%[0-9]+]]:fpr128 = SMULLv2i32_v2i64 [[COPY3]], [[COPY2]]
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; CHECK-NEXT: %mul:fpr128 = UZP2v4i32 [[SMULLv2i32_v2i64_]], [[SMULLv4i32_v2i64_]]
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; CHECK-NEXT: $q0 = COPY %mul
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; CHECK-NEXT: RET_ReallyLR implicit $q0
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%0:fpr(<4 x s32>) = COPY $q0
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%1:fpr(<4 x s32>) = COPY $q1
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%mul:fpr(<4 x s32>) = G_SMULH %0, %1
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$q0 = COPY %mul(<4 x s32>)
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RET_ReallyLR implicit $q0
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...
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