68 lines
2.7 KiB
LLVM
68 lines
2.7 KiB
LLVM
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; RUN: llc < %s | FileCheck %s
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; Derived from
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; #include <arm_sve.h>
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; void g();
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; svboolx2_t f0(int64_t i, int64_t n) {
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; svboolx2_t r = svwhilelt_b16_x2(i, n);
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; g();
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; return r;
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; }
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; svboolx2_t f1(svcount_t n) {
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; svboolx2_t r = svpext_lane_c8_x2(n, 1);
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; g();
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; return r;
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; }
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;
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; Check that predicate register pairs are spilled/filled without an ICE in the backend.
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target triple = "aarch64-unknown-linux"
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define <vscale x 32 x i1> @f0(i64 %i, i64 %n) #0 {
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entry:
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%0 = tail call { <vscale x 8 x i1>, <vscale x 8 x i1> } @llvm.aarch64.sve.whilelt.x2.nxv8i1(i64 %i, i64 %n)
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%1 = extractvalue { <vscale x 8 x i1>, <vscale x 8 x i1> } %0, 0
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%2 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %1)
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%3 = tail call <vscale x 32 x i1> @llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> poison, <vscale x 16 x i1> %2, i64 0)
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%4 = extractvalue { <vscale x 8 x i1>, <vscale x 8 x i1> } %0, 1
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%5 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
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%6 = tail call <vscale x 32 x i1> @llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> %3, <vscale x 16 x i1> %5, i64 16)
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tail call void @g()
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ret <vscale x 32 x i1> %6
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}
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; CHECK-LABEL: f0:
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; CHECK: whilelt { p0.h, p1.h }
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; CHECK: str p0, [sp, #6, mul vl]
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; CHECK: str p1, [sp, #7, mul vl]
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; CHECK: ldr p0, [sp, #6, mul vl]
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; CHECK: ldr p1, [sp, #7, mul vl]
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define <vscale x 32 x i1> @f1(target("aarch64.svcount") %n) #0 {
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entry:
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%0 = tail call { <vscale x 16 x i1>, <vscale x 16 x i1> } @llvm.aarch64.sve.pext.x2.nxv16i1(target("aarch64.svcount") %n, i32 1)
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%1 = extractvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %0, 0
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%2 = tail call <vscale x 32 x i1> @llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> poison, <vscale x 16 x i1> %1, i64 0)
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%3 = extractvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %0, 1
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%4 = tail call <vscale x 32 x i1> @llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> %2, <vscale x 16 x i1> %3, i64 16)
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tail call void @g()
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ret <vscale x 32 x i1> %4
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}
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; CHECK-LABEL: f1:
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; CHECK: pext { p0.b, p1.b }
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; CHECK: str p0, [sp, #6, mul vl]
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; CHECK: str p1, [sp, #7, mul vl]
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; CHECK: ldr p0, [sp, #6, mul vl]
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; CHECK: ldr p1, [sp, #7, mul vl]
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declare void @g(...)
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declare { <vscale x 8 x i1>, <vscale x 8 x i1> } @llvm.aarch64.sve.whilelt.x2.nxv8i1(i64, i64)
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declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>)
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declare <vscale x 32 x i1> @llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1>, <vscale x 16 x i1>, i64 immarg)
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declare { <vscale x 16 x i1>, <vscale x 16 x i1> } @llvm.aarch64.sve.pext.x2.nxv16i1(target("aarch64.svcount"), i32 immarg) #1
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attributes #0 = { nounwind "target-features"="+sve,+sve2,+sve2p1" }
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