280 lines
11 KiB
Text
280 lines
11 KiB
Text
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -start-before=si-lower-sgpr-spills -stop-after=virtregrewriter,1 -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
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# Tests to check the conservative lieness extension for the wwm registers during SGPR spill lowering.
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# Even though the VGPR can be shared for the wwm-operand (writelane/readlane get inserted for the SGPR spills)
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# and the regular operand (%0), they get different registers as we conservatively extend the liveness of the
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# wwm-operands.
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---
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name: test_single_block
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tracksRegLiveness: true
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frameInfo:
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maxAlignment: 4
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stack:
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- { id: 0, type: spill-slot, size: 4, alignment: 4, stack-id: sgpr-spill }
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machineFunctionInfo:
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isEntryFunction: false
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scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
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stackPtrOffsetReg: '$sgpr32'
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frameOffsetReg: '$sgpr33'
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hasSpilledSGPRs: true
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body: |
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bb.0:
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liveins: $sgpr4, $vgpr2_vgpr3
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; GCN-LABEL: name: test_single_block
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; GCN: liveins: $sgpr4, $vgpr2_vgpr3
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: renamable $vgpr0 = IMPLICIT_DEF
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; GCN-NEXT: renamable $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr4, 0, killed $vgpr0
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; GCN-NEXT: S_NOP 0
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; GCN-NEXT: $sgpr4 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 0
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; GCN-NEXT: renamable $vgpr1 = V_MOV_B32_e32 20, implicit $exec
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; GCN-NEXT: GLOBAL_STORE_DWORD $vgpr2_vgpr3, killed renamable $vgpr1, 0, 0, implicit $exec
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; GCN-NEXT: KILL killed renamable $vgpr0
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; GCN-NEXT: SI_RETURN
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SI_SPILL_S32_SAVE killed $sgpr4, %stack.0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr32
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S_NOP 0
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renamable $sgpr4 = SI_SPILL_S32_RESTORE %stack.0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr32
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%0:vgpr_32 = V_MOV_B32_e32 20, implicit $exec
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GLOBAL_STORE_DWORD $vgpr2_vgpr3, %0:vgpr_32, 0, 0, implicit $exec
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SI_RETURN
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...
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# Due to the presence of wwm-operand in the divergent flow, the regular variable (%0) shouldn't get the same register
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# allocated for the wwm-operand in writelane/readlane when the SGPR spill is lowered.
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---
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name: test_if_else
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tracksRegLiveness: true
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frameInfo:
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maxAlignment: 4
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stack:
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- { id: 0, type: spill-slot, size: 4, alignment: 4, stack-id: sgpr-spill }
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machineFunctionInfo:
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isEntryFunction: false
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scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
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stackPtrOffsetReg: '$sgpr32'
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frameOffsetReg: '$sgpr33'
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hasSpilledSGPRs: true
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body: |
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; GCN-LABEL: name: test_if_else
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; GCN: bb.0:
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; GCN-NEXT: successors: %bb.1(0x80000000)
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; GCN-NEXT: liveins: $sgpr6, $sgpr10_sgpr11
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: renamable $vgpr0 = IMPLICIT_DEF
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; GCN-NEXT: S_BRANCH %bb.1
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: bb.1:
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; GCN-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
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; GCN-NEXT: liveins: $sgpr6, $vgpr0, $sgpr10_sgpr11
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: renamable $vgpr1 = V_MOV_B32_e32 10, implicit $exec
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; GCN-NEXT: S_CBRANCH_EXECZ %bb.3, implicit $exec
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: bb.2:
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; GCN-NEXT: successors: %bb.3(0x80000000)
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; GCN-NEXT: liveins: $sgpr6, $vgpr0, $sgpr10_sgpr11
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: renamable $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr6, 0, killed $vgpr0
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; GCN-NEXT: S_NOP 0
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; GCN-NEXT: $sgpr6 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 0
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; GCN-NEXT: renamable $vgpr1 = V_MOV_B32_e32 20, implicit $exec
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; GCN-NEXT: S_BRANCH %bb.3
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: bb.3:
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; GCN-NEXT: liveins: $vgpr0, $vgpr1, $sgpr10_sgpr11
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: $sgpr5 = V_READFIRSTLANE_B32 killed $vgpr1, implicit $exec
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; GCN-NEXT: S_STORE_DWORD_IMM $sgpr5, $sgpr10_sgpr11, 0, 0
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; GCN-NEXT: KILL killed renamable $vgpr0
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; GCN-NEXT: SI_RETURN
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bb.0:
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liveins: $sgpr6, $sgpr10_sgpr11
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S_BRANCH %bb.1
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bb.1:
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liveins: $sgpr6, $sgpr10_sgpr11
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%0:vgpr_32 = V_MOV_B32_e32 10, implicit $exec
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S_CBRANCH_EXECZ %bb.3, implicit $exec
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bb.2:
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liveins: $sgpr6, $sgpr10_sgpr11
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SI_SPILL_S32_SAVE killed $sgpr6, %stack.0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr32
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S_NOP 0
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renamable $sgpr6 = SI_SPILL_S32_RESTORE %stack.0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr32
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%0:vgpr_32 = V_MOV_B32_e32 20, implicit $exec
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S_BRANCH %bb.3
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bb.3:
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liveins: $sgpr10_sgpr11
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$sgpr5 = V_READFIRSTLANE_B32 %0:vgpr_32, implicit $exec
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S_STORE_DWORD_IMM $sgpr5, $sgpr10_sgpr11, 0, 0
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SI_RETURN
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...
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# The wwm-register usage outside the loop should have the interference marked with
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# all the regular virtual registers used in the test. The divergent loop index value (%1)
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# can actually share the same VGPR as the wwm-operand. But since we extend the liveness of
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# the wwm operand, an interference will always exist between them.
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---
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name: test_loop
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tracksRegLiveness: true
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frameInfo:
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maxAlignment: 4
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stack:
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- { id: 0, type: spill-slot, size: 4, alignment: 4, stack-id: sgpr-spill }
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machineFunctionInfo:
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isEntryFunction: false
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scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
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stackPtrOffsetReg: '$sgpr32'
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frameOffsetReg: '$sgpr33'
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hasSpilledSGPRs: true
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body: |
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; GCN-LABEL: name: test_loop
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; GCN: bb.0:
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; GCN-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
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; GCN-NEXT: liveins: $sgpr4, $sgpr10_sgpr11
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: renamable $vgpr0 = IMPLICIT_DEF
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; GCN-NEXT: renamable $vgpr1 = V_MOV_B32_e32 10, implicit $exec
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; GCN-NEXT: S_CBRANCH_EXECZ %bb.2, implicit $exec
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: bb.1:
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; GCN-NEXT: successors: %bb.2(0x80000000)
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; GCN-NEXT: liveins: $sgpr4, $vgpr0, $sgpr10_sgpr11
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: renamable $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr4, 0, killed $vgpr0
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; GCN-NEXT: S_NOP 0
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; GCN-NEXT: $sgpr4 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 0
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; GCN-NEXT: renamable $vgpr1 = V_MOV_B32_e32 20, implicit $exec
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; GCN-NEXT: S_BRANCH %bb.2
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: bb.2:
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; GCN-NEXT: successors: %bb.3(0x80000000)
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; GCN-NEXT: liveins: $sgpr4, $vgpr0, $vgpr1, $sgpr10_sgpr11
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: S_STORE_DWORD_IMM $sgpr4, $sgpr10_sgpr11, 0, 0
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; GCN-NEXT: $sgpr5 = V_READFIRSTLANE_B32 killed $vgpr1, implicit $exec
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; GCN-NEXT: S_STORE_DWORD_IMM $sgpr5, $sgpr10_sgpr11, 0, 4
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; GCN-NEXT: renamable $vgpr1 = V_MOV_B32_e32 5, implicit $exec
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; GCN-NEXT: S_CBRANCH_EXECZ %bb.3, implicit $exec
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; GCN-NEXT: S_BRANCH %bb.3
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: bb.3:
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; GCN-NEXT: successors: %bb.5(0x40000000), %bb.4(0x40000000)
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; GCN-NEXT: liveins: $vgpr0, $vgpr1
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: $vcc = V_CMP_EQ_U32_e64 0, $vgpr1, implicit $exec
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; GCN-NEXT: $sgpr6_sgpr7 = S_AND_SAVEEXEC_B64 $vcc, implicit-def $exec, implicit-def $scc, implicit $exec
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; GCN-NEXT: S_CBRANCH_SCC1 %bb.5, implicit $scc
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: bb.4:
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; GCN-NEXT: successors: %bb.3(0x80000000)
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; GCN-NEXT: liveins: $vgpr0, $vgpr1, $sgpr6_sgpr7
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: renamable $vgpr1 = V_SUB_U32_e32 1, killed $vgpr1, implicit $exec
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; GCN-NEXT: renamable $vgpr1 = V_MOV_B32_e32 killed $vgpr1, implicit $exec
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; GCN-NEXT: S_BRANCH %bb.3
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: bb.5:
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; GCN-NEXT: liveins: $vgpr0, $sgpr6_sgpr7
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: $exec = S_OR_B64 $exec, $sgpr6_sgpr7, implicit-def $scc
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; GCN-NEXT: KILL killed renamable $vgpr0
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; GCN-NEXT: SI_RETURN
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bb.0:
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liveins: $sgpr4, $sgpr10_sgpr11
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%0:vgpr_32 = V_MOV_B32_e32 10, implicit $exec
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S_CBRANCH_EXECZ %bb.2, implicit $exec
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bb.1:
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liveins: $sgpr4, $sgpr10_sgpr11
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SI_SPILL_S32_SAVE killed $sgpr4, %stack.0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr32
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S_NOP 0
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renamable $sgpr4 = SI_SPILL_S32_RESTORE %stack.0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr32
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%0:vgpr_32 = V_MOV_B32_e32 20, implicit $exec
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S_BRANCH %bb.2
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bb.2:
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liveins: $sgpr4, $sgpr10_sgpr11
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S_STORE_DWORD_IMM $sgpr4, $sgpr10_sgpr11, 0, 0
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$sgpr5 = V_READFIRSTLANE_B32 %0:vgpr_32, implicit $exec
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S_STORE_DWORD_IMM $sgpr5, $sgpr10_sgpr11, 0, 4
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%1:vgpr_32 = V_MOV_B32_e32 5, implicit $exec
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S_CBRANCH_EXECZ %bb.3, implicit $exec
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S_BRANCH %bb.3
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bb.3:
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$vcc = V_CMP_EQ_U32_e64 0, %1:vgpr_32, implicit $exec
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$sgpr6_sgpr7 = S_AND_SAVEEXEC_B64 $vcc, implicit-def $exec, implicit-def $scc, implicit $exec
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S_CBRANCH_SCC1 %bb.5, implicit $scc
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bb.4:
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liveins: $sgpr6_sgpr7
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%2:vgpr_32 = V_SUB_U32_e32 1, %1:vgpr_32, implicit $exec
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%1:vgpr_32 = V_MOV_B32_e32 %2:vgpr_32, implicit $exec
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S_BRANCH %bb.3
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bb.5:
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liveins: $sgpr6_sgpr7
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$exec = S_OR_B64 $exec, $sgpr6_sgpr7, implicit-def $scc
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SI_RETURN
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...
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# There must be one KILL instruction for the wwm-operand in every return block.
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# Due to that, the wwm-register allocated should be different from the ones
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# allocated for the regular virtual registers.
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---
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name: test_multiple_return_blocks
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tracksRegLiveness: true
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frameInfo:
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maxAlignment: 4
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stack:
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- { id: 0, type: spill-slot, size: 4, alignment: 4, stack-id: sgpr-spill }
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machineFunctionInfo:
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isEntryFunction: false
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scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
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stackPtrOffsetReg: '$sgpr32'
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frameOffsetReg: '$sgpr33'
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hasSpilledSGPRs: true
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body: |
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; GCN-LABEL: name: test_multiple_return_blocks
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; GCN: bb.0:
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; GCN-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
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; GCN-NEXT: liveins: $sgpr4, $vgpr2_vgpr3
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: renamable $vgpr0 = IMPLICIT_DEF
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; GCN-NEXT: S_CBRANCH_EXECZ %bb.2, implicit $exec
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: bb.1:
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; GCN-NEXT: liveins: $sgpr4, $vgpr0, $vgpr2_vgpr3
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: renamable $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr4, 0, killed $vgpr0
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; GCN-NEXT: S_NOP 0
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; GCN-NEXT: $sgpr4 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 0
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; GCN-NEXT: renamable $vgpr1 = V_MOV_B32_e32 10, implicit $exec
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; GCN-NEXT: GLOBAL_STORE_DWORD $vgpr2_vgpr3, killed renamable $vgpr1, 0, 0, implicit $exec
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; GCN-NEXT: KILL killed renamable $vgpr0
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; GCN-NEXT: SI_RETURN
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: bb.2:
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; GCN-NEXT: liveins: $vgpr0, $vgpr2_vgpr3
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: renamable $vgpr1 = V_MOV_B32_e32 20, implicit $exec
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; GCN-NEXT: GLOBAL_STORE_DWORD $vgpr2_vgpr3, killed renamable $vgpr1, 0, 0, implicit $exec
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; GCN-NEXT: KILL killed renamable $vgpr0
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; GCN-NEXT: SI_RETURN
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bb.0:
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liveins: $sgpr4, $vgpr2_vgpr3
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S_CBRANCH_EXECZ %bb.2, implicit $exec
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bb.1:
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liveins: $sgpr4, $vgpr2_vgpr3
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SI_SPILL_S32_SAVE killed $sgpr4, %stack.0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr32
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S_NOP 0
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renamable $sgpr4 = SI_SPILL_S32_RESTORE %stack.0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr32
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%0:vgpr_32 = V_MOV_B32_e32 10, implicit $exec
|
||
|
|
GLOBAL_STORE_DWORD $vgpr2_vgpr3, %0:vgpr_32, 0, 0, implicit $exec
|
||
|
|
SI_RETURN
|
||
|
|
bb.2:
|
||
|
|
liveins: $vgpr2_vgpr3
|
||
|
|
%1:vgpr_32 = V_MOV_B32_e32 20, implicit $exec
|
||
|
|
GLOBAL_STORE_DWORD $vgpr2_vgpr3, %1:vgpr_32, 0, 0, implicit $exec
|
||
|
|
SI_RETURN
|
||
|
|
...
|