617 lines
24 KiB
LLVM
617 lines
24 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck %s
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; LDS is allocated per-kernel. Module scope variables are gathered into a struct which is
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; allocated at address zero, if used by the kernel. Kernel scope variables are gathered into
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; a per-kernel struct and allocated immediately after the module scope.
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; This test checks that the module and kernel scope variables are allocated in deterministic
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; order without spurious alignment padding between the two
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; External LDS is checked because it influences LDS padding in general and because it will
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; not be moved into either module or kernel struct
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@module_variable = addrspace(3) global i16 undef
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; Variables are allocated into module scope block when used by a non-kernel function
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define void @use_module() #0 {
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; CHECK-LABEL: use_module:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_mov_b32_e32 v0, 0
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; CHECK-NEXT: ds_write_b16 v0, v0
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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store i16 0, ptr addrspace(3) @module_variable
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ret void
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}
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; Variables only used by kernels are specialised and allocated per-kernel
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@kernel_normal = addrspace(3) global i16 undef
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@kernel_overalign = addrspace(3) global i16 undef, align 4
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; External LDS shall not introduce padding between module and kernel scope variables
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@extern_normal = external addrspace(3) global [0 x float]
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@extern_overalign = external addrspace(3) global [0 x float], align 8
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; External LDS does not influence the frame when called indirectly either
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define void @use_extern_normal() #0 {
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; CHECK-LABEL: use_extern_normal:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: s_getpc_b64 s[6:7]
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; CHECK-NEXT: s_add_u32 s6, s6, llvm.amdgcn.dynlds.offset.table@rel32@lo+4
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; CHECK-NEXT: s_addc_u32 s7, s7, llvm.amdgcn.dynlds.offset.table@rel32@hi+12
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; CHECK-NEXT: s_mov_b32 s4, s15
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; CHECK-NEXT: s_ashr_i32 s5, s15, 31
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; CHECK-NEXT: v_mov_b32_e32 v0, 0x4048f5c3
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; CHECK-NEXT: s_lshl_b64 s[4:5], s[4:5], 2
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; CHECK-NEXT: s_add_u32 s4, s4, s6
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; CHECK-NEXT: s_addc_u32 s5, s5, s7
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; CHECK-NEXT: s_load_dword s4, s[4:5], 0x0
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: v_mov_b32_e32 v1, s4
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; CHECK-NEXT: ds_write_b32 v1, v0
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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%arrayidx = getelementptr inbounds [0 x float], ptr addrspace(3) @extern_normal, i32 0, i32 0
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store float 0x40091EB860000000, ptr addrspace(3) %arrayidx
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ret void
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}
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define void @use_extern_overalign() #0 {
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; CHECK-LABEL: use_extern_overalign:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: s_getpc_b64 s[6:7]
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; CHECK-NEXT: s_add_u32 s6, s6, llvm.amdgcn.dynlds.offset.table@rel32@lo+4
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; CHECK-NEXT: s_addc_u32 s7, s7, llvm.amdgcn.dynlds.offset.table@rel32@hi+12
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; CHECK-NEXT: s_mov_b32 s4, s15
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; CHECK-NEXT: s_ashr_i32 s5, s15, 31
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; CHECK-NEXT: v_mov_b32_e32 v0, 0x42280000
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; CHECK-NEXT: s_lshl_b64 s[4:5], s[4:5], 2
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; CHECK-NEXT: s_add_u32 s4, s4, s6
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; CHECK-NEXT: s_addc_u32 s5, s5, s7
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; CHECK-NEXT: s_load_dword s4, s[4:5], 0x0
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: v_mov_b32_e32 v1, s4
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; CHECK-NEXT: ds_write_b32 v1, v0 offset:4
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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%arrayidx = getelementptr inbounds [0 x float], ptr addrspace(3) @extern_overalign, i32 0, i32 1
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store float 4.200000e+01, ptr addrspace(3) %arrayidx
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ret void
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}
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; First 2^3 of 2^4 cases encoded into function names
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; no use of extern variable from nested function
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; module_variable used/not-used
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; kernel variable normal/overaligned
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; extern variable normal/overaligned
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define amdgpu_kernel void @module_0_kernel_normal_extern_normal(i32 %idx) {
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; CHECK-LABEL: module_0_kernel_normal_extern_normal:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_load_dword s0, s[4:5], 0x0
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; CHECK-NEXT: v_mov_b32_e32 v0, 0
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; CHECK-NEXT: v_mov_b32_e32 v1, 2
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: s_lshl_b32 s0, s0, 2
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; CHECK-NEXT: s_add_i32 s0, s0, 4
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; CHECK-NEXT: v_mov_b32_e32 v2, s0
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; CHECK-NEXT: ds_write_b16 v0, v1
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; CHECK-NEXT: ds_write_b32 v2, v0
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; CHECK-NEXT: s_endpgm
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store i16 2, ptr addrspace(3) @kernel_normal
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%arrayidx1 = getelementptr inbounds [0 x float], ptr addrspace(3) @extern_normal, i32 0, i32 %idx
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store float 0.0, ptr addrspace(3) %arrayidx1
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ret void
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}
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define amdgpu_kernel void @module_1_kernel_normal_extern_normal(i32 %idx) {
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; CHECK-LABEL: module_1_kernel_normal_extern_normal:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_add_u32 s6, s6, s9
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; CHECK-NEXT: s_mov_b32 s32, 0
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; CHECK-NEXT: s_addc_u32 s7, s7, 0
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; CHECK-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s6
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; CHECK-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s7
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; CHECK-NEXT: s_add_u32 s0, s0, s9
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; CHECK-NEXT: s_addc_u32 s1, s1, 0
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; CHECK-NEXT: s_add_u32 s8, s4, 8
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; CHECK-NEXT: s_addc_u32 s9, s5, 0
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; CHECK-NEXT: s_getpc_b64 s[6:7]
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; CHECK-NEXT: s_add_u32 s6, s6, use_module@gotpcrel32@lo+4
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; CHECK-NEXT: s_addc_u32 s7, s7, use_module@gotpcrel32@hi+12
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; CHECK-NEXT: s_load_dwordx2 s[10:11], s[6:7], 0x0
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; CHECK-NEXT: s_load_dword s12, s[4:5], 0x0
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: s_swappc_b64 s[30:31], s[10:11]
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; CHECK-NEXT: s_lshl_b32 s4, s12, 2
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; CHECK-NEXT: v_mov_b32_e32 v0, 0
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; CHECK-NEXT: v_mov_b32_e32 v1, 1
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; CHECK-NEXT: s_add_i32 s4, s4, 4
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; CHECK-NEXT: v_mov_b32_e32 v2, 2
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; CHECK-NEXT: v_mov_b32_e32 v3, s4
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; CHECK-NEXT: ds_write_b16 v0, v1
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; CHECK-NEXT: ds_write_b16 v0, v2 offset:2
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; CHECK-NEXT: ds_write_b32 v3, v0
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; CHECK-NEXT: s_endpgm
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call void @use_module()
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store i16 1, ptr addrspace(3) @module_variable
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store i16 2, ptr addrspace(3) @kernel_normal
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%arrayidx1 = getelementptr inbounds [0 x float], ptr addrspace(3) @extern_normal, i32 0, i32 %idx
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store float 0.0, ptr addrspace(3) %arrayidx1
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ret void
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}
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define amdgpu_kernel void @module_0_kernel_overalign_extern_normal(i32 %idx) {
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; CHECK-LABEL: module_0_kernel_overalign_extern_normal:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_load_dword s0, s[4:5], 0x0
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; CHECK-NEXT: v_mov_b32_e32 v0, 0
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; CHECK-NEXT: v_mov_b32_e32 v1, 2
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: s_lshl_b32 s0, s0, 2
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; CHECK-NEXT: s_add_i32 s0, s0, 4
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; CHECK-NEXT: v_mov_b32_e32 v2, s0
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; CHECK-NEXT: ds_write_b16 v0, v1
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; CHECK-NEXT: ds_write_b32 v2, v0
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; CHECK-NEXT: s_endpgm
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store i16 2, ptr addrspace(3) @kernel_overalign
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%arrayidx1 = getelementptr inbounds [0 x float], ptr addrspace(3) @extern_normal, i32 0, i32 %idx
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store float 0.0, ptr addrspace(3) %arrayidx1
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ret void
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}
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define amdgpu_kernel void @module_1_kernel_overalign_extern_normal(i32 %idx) {
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; CHECK-LABEL: module_1_kernel_overalign_extern_normal:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_add_u32 s6, s6, s9
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; CHECK-NEXT: s_mov_b32 s32, 0
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; CHECK-NEXT: s_addc_u32 s7, s7, 0
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; CHECK-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s6
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; CHECK-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s7
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; CHECK-NEXT: s_add_u32 s0, s0, s9
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; CHECK-NEXT: s_addc_u32 s1, s1, 0
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; CHECK-NEXT: s_add_u32 s8, s4, 8
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; CHECK-NEXT: s_addc_u32 s9, s5, 0
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; CHECK-NEXT: s_getpc_b64 s[6:7]
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; CHECK-NEXT: s_add_u32 s6, s6, use_module@gotpcrel32@lo+4
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; CHECK-NEXT: s_addc_u32 s7, s7, use_module@gotpcrel32@hi+12
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; CHECK-NEXT: s_load_dwordx2 s[10:11], s[6:7], 0x0
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; CHECK-NEXT: s_load_dword s12, s[4:5], 0x0
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: s_swappc_b64 s[30:31], s[10:11]
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; CHECK-NEXT: s_lshl_b32 s4, s12, 2
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; CHECK-NEXT: v_mov_b32_e32 v0, 0
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; CHECK-NEXT: v_mov_b32_e32 v1, 1
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; CHECK-NEXT: s_add_i32 s4, s4, 8
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; CHECK-NEXT: v_mov_b32_e32 v2, 2
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; CHECK-NEXT: v_mov_b32_e32 v3, s4
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; CHECK-NEXT: ds_write_b16 v0, v1
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; CHECK-NEXT: ds_write_b16 v0, v2 offset:4
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; CHECK-NEXT: ds_write_b32 v3, v0
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; CHECK-NEXT: s_endpgm
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call void @use_module()
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store i16 1, ptr addrspace(3) @module_variable
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store i16 2, ptr addrspace(3) @kernel_overalign
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%arrayidx1 = getelementptr inbounds [0 x float], ptr addrspace(3) @extern_normal, i32 0, i32 %idx
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store float 0.0, ptr addrspace(3) %arrayidx1
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ret void
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}
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define amdgpu_kernel void @module_0_kernel_normal_extern_overalign(i32 %idx) {
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; CHECK-LABEL: module_0_kernel_normal_extern_overalign:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_load_dword s0, s[4:5], 0x0
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; CHECK-NEXT: v_mov_b32_e32 v0, 0
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; CHECK-NEXT: v_mov_b32_e32 v1, 2
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: s_lshl_b32 s0, s0, 2
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; CHECK-NEXT: s_add_i32 s0, s0, 8
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; CHECK-NEXT: v_mov_b32_e32 v2, s0
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; CHECK-NEXT: ds_write_b16 v0, v1
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; CHECK-NEXT: ds_write_b32 v2, v0
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; CHECK-NEXT: s_endpgm
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store i16 2, ptr addrspace(3) @kernel_normal
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%arrayidx1 = getelementptr inbounds [0 x float], ptr addrspace(3) @extern_overalign, i32 0, i32 %idx
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store float 0.0, ptr addrspace(3) %arrayidx1
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ret void
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}
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define amdgpu_kernel void @module_1_kernel_normal_extern_overalign(i32 %idx) {
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; CHECK-LABEL: module_1_kernel_normal_extern_overalign:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_add_u32 s6, s6, s9
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; CHECK-NEXT: s_mov_b32 s32, 0
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; CHECK-NEXT: s_addc_u32 s7, s7, 0
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; CHECK-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s6
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; CHECK-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s7
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; CHECK-NEXT: s_add_u32 s0, s0, s9
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; CHECK-NEXT: s_addc_u32 s1, s1, 0
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; CHECK-NEXT: s_add_u32 s8, s4, 8
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; CHECK-NEXT: s_addc_u32 s9, s5, 0
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; CHECK-NEXT: s_getpc_b64 s[6:7]
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; CHECK-NEXT: s_add_u32 s6, s6, use_module@gotpcrel32@lo+4
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; CHECK-NEXT: s_addc_u32 s7, s7, use_module@gotpcrel32@hi+12
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; CHECK-NEXT: s_load_dwordx2 s[10:11], s[6:7], 0x0
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; CHECK-NEXT: s_load_dword s12, s[4:5], 0x0
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: s_swappc_b64 s[30:31], s[10:11]
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; CHECK-NEXT: s_lshl_b32 s4, s12, 2
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; CHECK-NEXT: v_mov_b32_e32 v0, 0
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; CHECK-NEXT: v_mov_b32_e32 v1, 1
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; CHECK-NEXT: s_add_i32 s4, s4, 8
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; CHECK-NEXT: v_mov_b32_e32 v2, 2
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; CHECK-NEXT: v_mov_b32_e32 v3, s4
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; CHECK-NEXT: ds_write_b16 v0, v1
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; CHECK-NEXT: ds_write_b16 v0, v2 offset:2
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; CHECK-NEXT: ds_write_b32 v3, v0
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; CHECK-NEXT: s_endpgm
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call void @use_module()
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store i16 1, ptr addrspace(3) @module_variable
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store i16 2, ptr addrspace(3) @kernel_normal
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%arrayidx1 = getelementptr inbounds [0 x float], ptr addrspace(3) @extern_overalign, i32 0, i32 %idx
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store float 0.0, ptr addrspace(3) %arrayidx1
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ret void
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}
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define amdgpu_kernel void @module_0_kernel_overalign_extern_overalign(i32 %idx) {
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; CHECK-LABEL: module_0_kernel_overalign_extern_overalign:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_load_dword s0, s[4:5], 0x0
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|
|
; CHECK-NEXT: v_mov_b32_e32 v0, 0
|
||
|
|
; CHECK-NEXT: v_mov_b32_e32 v1, 2
|
||
|
|
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
|
||
|
|
; CHECK-NEXT: s_lshl_b32 s0, s0, 2
|
||
|
|
; CHECK-NEXT: s_add_i32 s0, s0, 8
|
||
|
|
; CHECK-NEXT: v_mov_b32_e32 v2, s0
|
||
|
|
; CHECK-NEXT: ds_write_b16 v0, v1
|
||
|
|
; CHECK-NEXT: ds_write_b32 v2, v0
|
||
|
|
; CHECK-NEXT: s_endpgm
|
||
|
|
store i16 2, ptr addrspace(3) @kernel_overalign
|
||
|
|
|
||
|
|
%arrayidx1 = getelementptr inbounds [0 x float], ptr addrspace(3) @extern_overalign, i32 0, i32 %idx
|
||
|
|
store float 0.0, ptr addrspace(3) %arrayidx1
|
||
|
|
ret void
|
||
|
|
}
|
||
|
|
|
||
|
|
define amdgpu_kernel void @module_1_kernel_overalign_extern_overalign(i32 %idx) {
|
||
|
|
; CHECK-LABEL: module_1_kernel_overalign_extern_overalign:
|
||
|
|
; CHECK: ; %bb.0:
|
||
|
|
; CHECK-NEXT: s_add_u32 s6, s6, s9
|
||
|
|
; CHECK-NEXT: s_mov_b32 s32, 0
|
||
|
|
; CHECK-NEXT: s_addc_u32 s7, s7, 0
|
||
|
|
; CHECK-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s6
|
||
|
|
; CHECK-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s7
|
||
|
|
; CHECK-NEXT: s_add_u32 s0, s0, s9
|
||
|
|
; CHECK-NEXT: s_addc_u32 s1, s1, 0
|
||
|
|
; CHECK-NEXT: s_add_u32 s8, s4, 8
|
||
|
|
; CHECK-NEXT: s_addc_u32 s9, s5, 0
|
||
|
|
; CHECK-NEXT: s_getpc_b64 s[6:7]
|
||
|
|
; CHECK-NEXT: s_add_u32 s6, s6, use_module@gotpcrel32@lo+4
|
||
|
|
; CHECK-NEXT: s_addc_u32 s7, s7, use_module@gotpcrel32@hi+12
|
||
|
|
; CHECK-NEXT: s_load_dwordx2 s[10:11], s[6:7], 0x0
|
||
|
|
; CHECK-NEXT: s_load_dword s12, s[4:5], 0x0
|
||
|
|
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
|
||
|
|
; CHECK-NEXT: s_swappc_b64 s[30:31], s[10:11]
|
||
|
|
; CHECK-NEXT: s_lshl_b32 s4, s12, 2
|
||
|
|
; CHECK-NEXT: v_mov_b32_e32 v0, 0
|
||
|
|
; CHECK-NEXT: v_mov_b32_e32 v1, 1
|
||
|
|
; CHECK-NEXT: s_add_i32 s4, s4, 8
|
||
|
|
; CHECK-NEXT: v_mov_b32_e32 v2, 2
|
||
|
|
; CHECK-NEXT: v_mov_b32_e32 v3, s4
|
||
|
|
; CHECK-NEXT: ds_write_b16 v0, v1
|
||
|
|
; CHECK-NEXT: ds_write_b16 v0, v2 offset:4
|
||
|
|
; CHECK-NEXT: ds_write_b32 v3, v0
|
||
|
|
; CHECK-NEXT: s_endpgm
|
||
|
|
call void @use_module()
|
||
|
|
store i16 1, ptr addrspace(3) @module_variable
|
||
|
|
|
||
|
|
store i16 2, ptr addrspace(3) @kernel_overalign
|
||
|
|
|
||
|
|
%arrayidx1 = getelementptr inbounds [0 x float], ptr addrspace(3) @extern_overalign, i32 0, i32 %idx
|
||
|
|
store float 0.0, ptr addrspace(3) %arrayidx1
|
||
|
|
ret void
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
;; Second 2^3 of 2^4 cases encoded into function names
|
||
|
|
; with extern variable from nested function
|
||
|
|
; module_variable used/not-used
|
||
|
|
; kernel variable normal/overaligned
|
||
|
|
; extern variable normal/overaligned
|
||
|
|
|
||
|
|
define amdgpu_kernel void @module_0_kernel_normal_indirect_extern_normal(i32 %idx) {
|
||
|
|
; CHECK-LABEL: module_0_kernel_normal_indirect_extern_normal:
|
||
|
|
; CHECK: ; %bb.0:
|
||
|
|
; CHECK-NEXT: s_add_u32 s6, s6, s9
|
||
|
|
; CHECK-NEXT: s_mov_b32 s32, 0
|
||
|
|
; CHECK-NEXT: s_addc_u32 s7, s7, 0
|
||
|
|
; CHECK-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s6
|
||
|
|
; CHECK-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s7
|
||
|
|
; CHECK-NEXT: s_add_u32 s0, s0, s9
|
||
|
|
; CHECK-NEXT: s_addc_u32 s1, s1, 0
|
||
|
|
; CHECK-NEXT: s_add_u32 s8, s4, 8
|
||
|
|
; CHECK-NEXT: s_addc_u32 s9, s5, 0
|
||
|
|
; CHECK-NEXT: s_getpc_b64 s[4:5]
|
||
|
|
; CHECK-NEXT: s_add_u32 s4, s4, use_extern_normal@gotpcrel32@lo+4
|
||
|
|
; CHECK-NEXT: s_addc_u32 s5, s5, use_extern_normal@gotpcrel32@hi+12
|
||
|
|
; CHECK-NEXT: v_mov_b32_e32 v0, 0
|
||
|
|
; CHECK-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
|
||
|
|
; CHECK-NEXT: v_mov_b32_e32 v1, 2
|
||
|
|
; CHECK-NEXT: s_mov_b32 s15, 0
|
||
|
|
; CHECK-NEXT: ds_write_b16 v0, v1
|
||
|
|
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
|
||
|
|
; CHECK-NEXT: s_swappc_b64 s[30:31], s[4:5]
|
||
|
|
; CHECK-NEXT: s_endpgm
|
||
|
|
store i16 2, ptr addrspace(3) @kernel_normal
|
||
|
|
|
||
|
|
call void @use_extern_normal()
|
||
|
|
ret void
|
||
|
|
}
|
||
|
|
|
||
|
|
define amdgpu_kernel void @module_1_kernel_normal_indirect_extern_normal(i32 %idx) {
|
||
|
|
; CHECK-LABEL: module_1_kernel_normal_indirect_extern_normal:
|
||
|
|
; CHECK: ; %bb.0:
|
||
|
|
; CHECK-NEXT: s_add_u32 s6, s6, s9
|
||
|
|
; CHECK-NEXT: s_mov_b32 s32, 0
|
||
|
|
; CHECK-NEXT: s_addc_u32 s7, s7, 0
|
||
|
|
; CHECK-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s6
|
||
|
|
; CHECK-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s7
|
||
|
|
; CHECK-NEXT: s_add_u32 s0, s0, s9
|
||
|
|
; CHECK-NEXT: s_addc_u32 s1, s1, 0
|
||
|
|
; CHECK-NEXT: s_add_u32 s8, s4, 8
|
||
|
|
; CHECK-NEXT: s_addc_u32 s9, s5, 0
|
||
|
|
; CHECK-NEXT: s_getpc_b64 s[4:5]
|
||
|
|
; CHECK-NEXT: s_add_u32 s4, s4, use_module@gotpcrel32@lo+4
|
||
|
|
; CHECK-NEXT: s_addc_u32 s5, s5, use_module@gotpcrel32@hi+12
|
||
|
|
; CHECK-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
|
||
|
|
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
|
||
|
|
; CHECK-NEXT: s_swappc_b64 s[30:31], s[4:5]
|
||
|
|
; CHECK-NEXT: s_getpc_b64 s[4:5]
|
||
|
|
; CHECK-NEXT: s_add_u32 s4, s4, use_extern_normal@gotpcrel32@lo+4
|
||
|
|
; CHECK-NEXT: s_addc_u32 s5, s5, use_extern_normal@gotpcrel32@hi+12
|
||
|
|
; CHECK-NEXT: v_mov_b32_e32 v0, 0
|
||
|
|
; CHECK-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
|
||
|
|
; CHECK-NEXT: v_mov_b32_e32 v1, 1
|
||
|
|
; CHECK-NEXT: v_mov_b32_e32 v2, 2
|
||
|
|
; CHECK-NEXT: s_mov_b32 s15, 4
|
||
|
|
; CHECK-NEXT: ds_write_b16 v0, v1
|
||
|
|
; CHECK-NEXT: ds_write_b16 v0, v2 offset:2
|
||
|
|
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
|
||
|
|
; CHECK-NEXT: s_swappc_b64 s[30:31], s[4:5]
|
||
|
|
; CHECK-NEXT: s_endpgm
|
||
|
|
call void @use_module()
|
||
|
|
store i16 1, ptr addrspace(3) @module_variable
|
||
|
|
|
||
|
|
store i16 2, ptr addrspace(3) @kernel_normal
|
||
|
|
|
||
|
|
call void @use_extern_normal()
|
||
|
|
ret void
|
||
|
|
}
|
||
|
|
|
||
|
|
define amdgpu_kernel void @module_0_kernel_overalign_indirect_extern_normal(i32 %idx) {
|
||
|
|
; CHECK-LABEL: module_0_kernel_overalign_indirect_extern_normal:
|
||
|
|
; CHECK: ; %bb.0:
|
||
|
|
; CHECK-NEXT: s_add_u32 s6, s6, s9
|
||
|
|
; CHECK-NEXT: s_mov_b32 s32, 0
|
||
|
|
; CHECK-NEXT: s_addc_u32 s7, s7, 0
|
||
|
|
; CHECK-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s6
|
||
|
|
; CHECK-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s7
|
||
|
|
; CHECK-NEXT: s_add_u32 s0, s0, s9
|
||
|
|
; CHECK-NEXT: s_addc_u32 s1, s1, 0
|
||
|
|
; CHECK-NEXT: s_add_u32 s8, s4, 8
|
||
|
|
; CHECK-NEXT: s_addc_u32 s9, s5, 0
|
||
|
|
; CHECK-NEXT: s_getpc_b64 s[4:5]
|
||
|
|
; CHECK-NEXT: s_add_u32 s4, s4, use_extern_normal@gotpcrel32@lo+4
|
||
|
|
; CHECK-NEXT: s_addc_u32 s5, s5, use_extern_normal@gotpcrel32@hi+12
|
||
|
|
; CHECK-NEXT: v_mov_b32_e32 v0, 0
|
||
|
|
; CHECK-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
|
||
|
|
; CHECK-NEXT: v_mov_b32_e32 v1, 2
|
||
|
|
; CHECK-NEXT: s_mov_b32 s15, 2
|
||
|
|
; CHECK-NEXT: ds_write_b16 v0, v1
|
||
|
|
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
|
||
|
|
; CHECK-NEXT: s_swappc_b64 s[30:31], s[4:5]
|
||
|
|
; CHECK-NEXT: s_endpgm
|
||
|
|
store i16 2, ptr addrspace(3) @kernel_overalign
|
||
|
|
|
||
|
|
call void @use_extern_normal()
|
||
|
|
ret void
|
||
|
|
}
|
||
|
|
|
||
|
|
define amdgpu_kernel void @module_1_kernel_overalign_indirect_extern_normal(i32 %idx) {
|
||
|
|
; CHECK-LABEL: module_1_kernel_overalign_indirect_extern_normal:
|
||
|
|
; CHECK: ; %bb.0:
|
||
|
|
; CHECK-NEXT: s_add_u32 s6, s6, s9
|
||
|
|
; CHECK-NEXT: s_mov_b32 s32, 0
|
||
|
|
; CHECK-NEXT: s_addc_u32 s7, s7, 0
|
||
|
|
; CHECK-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s6
|
||
|
|
; CHECK-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s7
|
||
|
|
; CHECK-NEXT: s_add_u32 s0, s0, s9
|
||
|
|
; CHECK-NEXT: s_addc_u32 s1, s1, 0
|
||
|
|
; CHECK-NEXT: s_add_u32 s8, s4, 8
|
||
|
|
; CHECK-NEXT: s_addc_u32 s9, s5, 0
|
||
|
|
; CHECK-NEXT: s_getpc_b64 s[4:5]
|
||
|
|
; CHECK-NEXT: s_add_u32 s4, s4, use_module@gotpcrel32@lo+4
|
||
|
|
; CHECK-NEXT: s_addc_u32 s5, s5, use_module@gotpcrel32@hi+12
|
||
|
|
; CHECK-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
|
||
|
|
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
|
||
|
|
; CHECK-NEXT: s_swappc_b64 s[30:31], s[4:5]
|
||
|
|
; CHECK-NEXT: s_getpc_b64 s[4:5]
|
||
|
|
; CHECK-NEXT: s_add_u32 s4, s4, use_extern_normal@gotpcrel32@lo+4
|
||
|
|
; CHECK-NEXT: s_addc_u32 s5, s5, use_extern_normal@gotpcrel32@hi+12
|
||
|
|
; CHECK-NEXT: v_mov_b32_e32 v0, 0
|
||
|
|
; CHECK-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
|
||
|
|
; CHECK-NEXT: v_mov_b32_e32 v1, 1
|
||
|
|
; CHECK-NEXT: v_mov_b32_e32 v2, 2
|
||
|
|
; CHECK-NEXT: s_mov_b32 s15, 6
|
||
|
|
; CHECK-NEXT: ds_write_b16 v0, v1
|
||
|
|
; CHECK-NEXT: ds_write_b16 v0, v2 offset:4
|
||
|
|
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
|
||
|
|
; CHECK-NEXT: s_swappc_b64 s[30:31], s[4:5]
|
||
|
|
; CHECK-NEXT: s_endpgm
|
||
|
|
call void @use_module()
|
||
|
|
store i16 1, ptr addrspace(3) @module_variable
|
||
|
|
|
||
|
|
store i16 2, ptr addrspace(3) @kernel_overalign
|
||
|
|
|
||
|
|
call void @use_extern_normal()
|
||
|
|
ret void
|
||
|
|
}
|
||
|
|
|
||
|
|
define amdgpu_kernel void @module_0_kernel_normal_indirect_extern_overalign(i32 %idx) {
|
||
|
|
; CHECK-LABEL: module_0_kernel_normal_indirect_extern_overalign:
|
||
|
|
; CHECK: ; %bb.0:
|
||
|
|
; CHECK-NEXT: s_add_u32 s6, s6, s9
|
||
|
|
; CHECK-NEXT: s_mov_b32 s32, 0
|
||
|
|
; CHECK-NEXT: s_addc_u32 s7, s7, 0
|
||
|
|
; CHECK-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s6
|
||
|
|
; CHECK-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s7
|
||
|
|
; CHECK-NEXT: s_add_u32 s0, s0, s9
|
||
|
|
; CHECK-NEXT: s_addc_u32 s1, s1, 0
|
||
|
|
; CHECK-NEXT: s_add_u32 s8, s4, 8
|
||
|
|
; CHECK-NEXT: s_addc_u32 s9, s5, 0
|
||
|
|
; CHECK-NEXT: s_getpc_b64 s[4:5]
|
||
|
|
; CHECK-NEXT: s_add_u32 s4, s4, use_extern_overalign@gotpcrel32@lo+4
|
||
|
|
; CHECK-NEXT: s_addc_u32 s5, s5, use_extern_overalign@gotpcrel32@hi+12
|
||
|
|
; CHECK-NEXT: v_mov_b32_e32 v0, 0
|
||
|
|
; CHECK-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
|
||
|
|
; CHECK-NEXT: v_mov_b32_e32 v1, 2
|
||
|
|
; CHECK-NEXT: s_mov_b32 s15, 1
|
||
|
|
; CHECK-NEXT: ds_write_b16 v0, v1
|
||
|
|
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
|
||
|
|
; CHECK-NEXT: s_swappc_b64 s[30:31], s[4:5]
|
||
|
|
; CHECK-NEXT: s_endpgm
|
||
|
|
store i16 2, ptr addrspace(3) @kernel_normal
|
||
|
|
|
||
|
|
call void @use_extern_overalign()
|
||
|
|
ret void
|
||
|
|
}
|
||
|
|
|
||
|
|
define amdgpu_kernel void @module_1_kernel_normal_indirect_extern_overalign(i32 %idx) {
|
||
|
|
; CHECK-LABEL: module_1_kernel_normal_indirect_extern_overalign:
|
||
|
|
; CHECK: ; %bb.0:
|
||
|
|
; CHECK-NEXT: s_add_u32 s6, s6, s9
|
||
|
|
; CHECK-NEXT: s_mov_b32 s32, 0
|
||
|
|
; CHECK-NEXT: s_addc_u32 s7, s7, 0
|
||
|
|
; CHECK-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s6
|
||
|
|
; CHECK-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s7
|
||
|
|
; CHECK-NEXT: s_add_u32 s0, s0, s9
|
||
|
|
; CHECK-NEXT: s_addc_u32 s1, s1, 0
|
||
|
|
; CHECK-NEXT: s_add_u32 s8, s4, 8
|
||
|
|
; CHECK-NEXT: s_addc_u32 s9, s5, 0
|
||
|
|
; CHECK-NEXT: s_getpc_b64 s[4:5]
|
||
|
|
; CHECK-NEXT: s_add_u32 s4, s4, use_module@gotpcrel32@lo+4
|
||
|
|
; CHECK-NEXT: s_addc_u32 s5, s5, use_module@gotpcrel32@hi+12
|
||
|
|
; CHECK-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
|
||
|
|
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
|
||
|
|
; CHECK-NEXT: s_swappc_b64 s[30:31], s[4:5]
|
||
|
|
; CHECK-NEXT: s_getpc_b64 s[4:5]
|
||
|
|
; CHECK-NEXT: s_add_u32 s4, s4, use_extern_overalign@gotpcrel32@lo+4
|
||
|
|
; CHECK-NEXT: s_addc_u32 s5, s5, use_extern_overalign@gotpcrel32@hi+12
|
||
|
|
; CHECK-NEXT: v_mov_b32_e32 v0, 0
|
||
|
|
; CHECK-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
|
||
|
|
; CHECK-NEXT: v_mov_b32_e32 v1, 1
|
||
|
|
; CHECK-NEXT: v_mov_b32_e32 v2, 2
|
||
|
|
; CHECK-NEXT: s_mov_b32 s15, 5
|
||
|
|
; CHECK-NEXT: ds_write_b16 v0, v1
|
||
|
|
; CHECK-NEXT: ds_write_b16 v0, v2 offset:2
|
||
|
|
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
|
||
|
|
; CHECK-NEXT: s_swappc_b64 s[30:31], s[4:5]
|
||
|
|
; CHECK-NEXT: s_endpgm
|
||
|
|
call void @use_module()
|
||
|
|
store i16 1, ptr addrspace(3) @module_variable
|
||
|
|
|
||
|
|
store i16 2, ptr addrspace(3) @kernel_normal
|
||
|
|
|
||
|
|
call void @use_extern_overalign()
|
||
|
|
ret void
|
||
|
|
}
|
||
|
|
|
||
|
|
define amdgpu_kernel void @module_0_kernel_overalign_indirect_extern_overalign(i32 %idx) {
|
||
|
|
; CHECK-LABEL: module_0_kernel_overalign_indirect_extern_overalign:
|
||
|
|
; CHECK: ; %bb.0:
|
||
|
|
; CHECK-NEXT: s_add_u32 s6, s6, s9
|
||
|
|
; CHECK-NEXT: s_mov_b32 s32, 0
|
||
|
|
; CHECK-NEXT: s_addc_u32 s7, s7, 0
|
||
|
|
; CHECK-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s6
|
||
|
|
; CHECK-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s7
|
||
|
|
; CHECK-NEXT: s_add_u32 s0, s0, s9
|
||
|
|
; CHECK-NEXT: s_addc_u32 s1, s1, 0
|
||
|
|
; CHECK-NEXT: s_add_u32 s8, s4, 8
|
||
|
|
; CHECK-NEXT: s_addc_u32 s9, s5, 0
|
||
|
|
; CHECK-NEXT: s_getpc_b64 s[4:5]
|
||
|
|
; CHECK-NEXT: s_add_u32 s4, s4, use_extern_overalign@gotpcrel32@lo+4
|
||
|
|
; CHECK-NEXT: s_addc_u32 s5, s5, use_extern_overalign@gotpcrel32@hi+12
|
||
|
|
; CHECK-NEXT: v_mov_b32_e32 v0, 0
|
||
|
|
; CHECK-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
|
||
|
|
; CHECK-NEXT: v_mov_b32_e32 v1, 2
|
||
|
|
; CHECK-NEXT: s_mov_b32 s15, 3
|
||
|
|
; CHECK-NEXT: ds_write_b16 v0, v1
|
||
|
|
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
|
||
|
|
; CHECK-NEXT: s_swappc_b64 s[30:31], s[4:5]
|
||
|
|
; CHECK-NEXT: s_endpgm
|
||
|
|
store i16 2, ptr addrspace(3) @kernel_overalign
|
||
|
|
|
||
|
|
call void @use_extern_overalign()
|
||
|
|
ret void
|
||
|
|
}
|
||
|
|
|
||
|
|
define amdgpu_kernel void @module_1_kernel_overalign_indirect_extern_overalign(i32 %idx) {
|
||
|
|
; CHECK-LABEL: module_1_kernel_overalign_indirect_extern_overalign:
|
||
|
|
; CHECK: ; %bb.0:
|
||
|
|
; CHECK-NEXT: s_add_u32 s6, s6, s9
|
||
|
|
; CHECK-NEXT: s_mov_b32 s32, 0
|
||
|
|
; CHECK-NEXT: s_addc_u32 s7, s7, 0
|
||
|
|
; CHECK-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s6
|
||
|
|
; CHECK-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s7
|
||
|
|
; CHECK-NEXT: s_add_u32 s0, s0, s9
|
||
|
|
; CHECK-NEXT: s_addc_u32 s1, s1, 0
|
||
|
|
; CHECK-NEXT: s_add_u32 s8, s4, 8
|
||
|
|
; CHECK-NEXT: s_addc_u32 s9, s5, 0
|
||
|
|
; CHECK-NEXT: s_getpc_b64 s[4:5]
|
||
|
|
; CHECK-NEXT: s_add_u32 s4, s4, use_module@gotpcrel32@lo+4
|
||
|
|
; CHECK-NEXT: s_addc_u32 s5, s5, use_module@gotpcrel32@hi+12
|
||
|
|
; CHECK-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
|
||
|
|
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
|
||
|
|
; CHECK-NEXT: s_swappc_b64 s[30:31], s[4:5]
|
||
|
|
; CHECK-NEXT: s_getpc_b64 s[4:5]
|
||
|
|
; CHECK-NEXT: s_add_u32 s4, s4, use_extern_overalign@gotpcrel32@lo+4
|
||
|
|
; CHECK-NEXT: s_addc_u32 s5, s5, use_extern_overalign@gotpcrel32@hi+12
|
||
|
|
; CHECK-NEXT: v_mov_b32_e32 v0, 0
|
||
|
|
; CHECK-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
|
||
|
|
; CHECK-NEXT: v_mov_b32_e32 v1, 1
|
||
|
|
; CHECK-NEXT: v_mov_b32_e32 v2, 2
|
||
|
|
; CHECK-NEXT: s_mov_b32 s15, 7
|
||
|
|
; CHECK-NEXT: ds_write_b16 v0, v1
|
||
|
|
; CHECK-NEXT: ds_write_b16 v0, v2 offset:4
|
||
|
|
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
|
||
|
|
; CHECK-NEXT: s_swappc_b64 s[30:31], s[4:5]
|
||
|
|
; CHECK-NEXT: s_endpgm
|
||
|
|
call void @use_module()
|
||
|
|
store i16 1, ptr addrspace(3) @module_variable
|
||
|
|
|
||
|
|
store i16 2, ptr addrspace(3) @kernel_overalign
|
||
|
|
|
||
|
|
call void @use_extern_overalign()
|
||
|
|
ret void
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
attributes #0 = { noinline }
|
||
|
|
|
||
|
|
!llvm.module.flags = !{!0}
|
||
|
|
!0 = !{i32 1, !"amdgpu_code_object_version", i32 500}
|