345 lines
12 KiB
LLVM
345 lines
12 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
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; RUN: llc -mtriple=amdgcn -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX8 %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX10 %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX11 %s
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; FIXME: GFX9 should be producing v_mad_u16 instead of v_mad_legacy_u16.
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define amdgpu_kernel void @mad_u16(
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; GFX8-LABEL: mad_u16:
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; GFX8: ; %bb.0: ; %entry
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; GFX8-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
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; GFX8-NEXT: v_lshlrev_b32_e32 v4, 1, v0
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; GFX8-NEXT: s_waitcnt lgkmcnt(0)
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; GFX8-NEXT: v_mov_b32_e32 v1, s3
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; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v4
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; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
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; GFX8-NEXT: v_mov_b32_e32 v3, s5
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; GFX8-NEXT: v_add_u32_e32 v2, vcc, s4, v4
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; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
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; GFX8-NEXT: v_mov_b32_e32 v5, s7
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; GFX8-NEXT: v_add_u32_e32 v4, vcc, s6, v4
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; GFX8-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
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; GFX8-NEXT: flat_load_ushort v6, v[0:1] glc
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; GFX8-NEXT: s_waitcnt vmcnt(0)
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; GFX8-NEXT: flat_load_ushort v2, v[2:3] glc
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; GFX8-NEXT: s_waitcnt vmcnt(0)
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; GFX8-NEXT: flat_load_ushort v3, v[4:5] glc
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; GFX8-NEXT: s_waitcnt vmcnt(0)
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; GFX8-NEXT: v_mov_b32_e32 v0, s0
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; GFX8-NEXT: v_mov_b32_e32 v1, s1
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; GFX8-NEXT: v_mad_u16 v2, v6, v2, v3
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; GFX8-NEXT: flat_store_short v[0:1], v2
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; GFX8-NEXT: s_endpgm
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;
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; GFX9-LABEL: mad_u16:
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; GFX9: ; %bb.0: ; %entry
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; GFX9-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
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; GFX9-NEXT: v_lshlrev_b32_e32 v0, 1, v0
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: global_load_ushort v1, v0, s[2:3] glc
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: global_load_ushort v2, v0, s[4:5] glc
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: global_load_ushort v3, v0, s[6:7] glc
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: v_mov_b32_e32 v0, 0
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; GFX9-NEXT: v_mad_legacy_u16 v1, v1, v2, v3
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; GFX9-NEXT: global_store_short v0, v1, s[0:1]
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; GFX9-NEXT: s_endpgm
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;
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; GFX10-LABEL: mad_u16:
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; GFX10: ; %bb.0: ; %entry
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; GFX10-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
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; GFX10-NEXT: v_lshlrev_b32_e32 v0, 1, v0
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; GFX10-NEXT: s_waitcnt lgkmcnt(0)
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; GFX10-NEXT: global_load_ushort v1, v0, s[2:3] glc dlc
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; GFX10-NEXT: s_waitcnt vmcnt(0)
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; GFX10-NEXT: global_load_ushort v2, v0, s[4:5] glc dlc
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; GFX10-NEXT: s_waitcnt vmcnt(0)
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; GFX10-NEXT: global_load_ushort v3, v0, s[6:7] glc dlc
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; GFX10-NEXT: s_waitcnt vmcnt(0)
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; GFX10-NEXT: v_mov_b32_e32 v0, 0
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; GFX10-NEXT: v_mad_u16 v1, v1, v2, v3
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; GFX10-NEXT: global_store_short v0, v1, s[0:1]
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; GFX10-NEXT: s_endpgm
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;
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; GFX11-LABEL: mad_u16:
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; GFX11: ; %bb.0: ; %entry
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; GFX11-NEXT: s_load_b256 s[0:7], s[0:1], 0x24
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; GFX11-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_lshlrev_b32 v0, 1, v0
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; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-NEXT: global_load_u16 v1, v0, s[2:3] glc dlc
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; GFX11-NEXT: s_waitcnt vmcnt(0)
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; GFX11-NEXT: global_load_u16 v2, v0, s[4:5] glc dlc
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; GFX11-NEXT: s_waitcnt vmcnt(0)
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; GFX11-NEXT: global_load_u16 v0, v0, s[6:7] glc dlc
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; GFX11-NEXT: s_waitcnt vmcnt(0)
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; GFX11-NEXT: v_mad_u16 v0, v1, v2, v0
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; GFX11-NEXT: global_store_b16 v3, v0, s[0:1]
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; GFX11-NEXT: s_nop 0
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; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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; GFX11-NEXT: s_endpgm
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ptr addrspace(1) %r,
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ptr addrspace(1) %a,
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ptr addrspace(1) %b,
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ptr addrspace(1) %c) {
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entry:
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%a.gep = getelementptr inbounds i16, ptr addrspace(1) %a, i32 %tid
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%b.gep = getelementptr inbounds i16, ptr addrspace(1) %b, i32 %tid
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%c.gep = getelementptr inbounds i16, ptr addrspace(1) %c, i32 %tid
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%a.val = load volatile i16, ptr addrspace(1) %a.gep
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%b.val = load volatile i16, ptr addrspace(1) %b.gep
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%c.val = load volatile i16, ptr addrspace(1) %c.gep
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%m.val = mul i16 %a.val, %b.val
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%r.val = add i16 %m.val, %c.val
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store i16 %r.val, ptr addrspace(1) %r
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ret void
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}
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define i16 @v_mad_u16(i16 %arg0, i16 %arg1, i16 %arg2) {
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; GFX8-LABEL: v_mad_u16:
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; GFX8: ; %bb.0:
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; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX8-NEXT: v_mad_u16 v0, v0, v1, v2
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; GFX8-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX9-LABEL: v_mad_u16:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: v_mad_legacy_u16 v0, v0, v1, v2
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX10-LABEL: v_mad_u16:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX10-NEXT: v_mad_u16 v0, v0, v1, v2
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; GFX10-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX11-LABEL: v_mad_u16:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-NEXT: v_mad_u16 v0, v0, v1, v2
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; GFX11-NEXT: s_setpc_b64 s[30:31]
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%mul = mul i16 %arg0, %arg1
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%add = add i16 %mul, %arg2
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ret i16 %add
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}
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define i32 @v_mad_u16_zext(i16 %arg0, i16 %arg1, i16 %arg2) {
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; GFX8-LABEL: v_mad_u16_zext:
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; GFX8: ; %bb.0:
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; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX8-NEXT: v_mad_u16 v0, v0, v1, v2
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; GFX8-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX9-LABEL: v_mad_u16_zext:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: v_mad_legacy_u16 v0, v0, v1, v2
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX10-LABEL: v_mad_u16_zext:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX10-NEXT: v_mad_u16 v0, v0, v1, v2
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; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v0
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; GFX10-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX11-LABEL: v_mad_u16_zext:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-NEXT: v_mad_u16 v0, v0, v1, v2
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; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0
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; GFX11-NEXT: s_setpc_b64 s[30:31]
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%mul = mul i16 %arg0, %arg1
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%add = add i16 %mul, %arg2
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%zext = zext i16 %add to i32
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ret i32 %zext
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}
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define i64 @v_mad_u16_zext64(i16 %arg0, i16 %arg1, i16 %arg2) {
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; GFX8-LABEL: v_mad_u16_zext64:
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; GFX8: ; %bb.0:
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; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX8-NEXT: v_mad_u16 v0, v0, v1, v2
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; GFX8-NEXT: v_mov_b32_e32 v1, 0
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; GFX8-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX9-LABEL: v_mad_u16_zext64:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: v_mad_legacy_u16 v0, v0, v1, v2
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; GFX9-NEXT: v_mov_b32_e32 v1, 0
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX10-LABEL: v_mad_u16_zext64:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX10-NEXT: v_mad_u16 v0, v0, v1, v2
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; GFX10-NEXT: v_mov_b32_e32 v1, 0
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; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v0
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; GFX10-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX11-LABEL: v_mad_u16_zext64:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-NEXT: v_mad_u16 v0, v0, v1, v2
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; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0xffff, v0
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; GFX11-NEXT: s_setpc_b64 s[30:31]
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%mul = mul i16 %arg0, %arg1
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%add = add i16 %mul, %arg2
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%zext = zext i16 %add to i64
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ret i64 %zext
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}
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define amdgpu_ps i16 @s_mad_u16(i16 inreg %arg0, i16 inreg %arg1, i16 inreg %arg2) {
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; GFX8-LABEL: s_mad_u16:
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; GFX8: ; %bb.0:
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; GFX8-NEXT: s_mul_i32 s0, s0, s1
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; GFX8-NEXT: s_add_i32 s0, s0, s2
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; GFX8-NEXT: ; return to shader part epilog
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;
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; GFX9-LABEL: s_mad_u16:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_mul_i32 s0, s0, s1
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; GFX9-NEXT: s_add_i32 s0, s0, s2
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: s_mad_u16:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_mul_i32 s0, s0, s1
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; GFX10-NEXT: s_add_i32 s0, s0, s2
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; GFX10-NEXT: ; return to shader part epilog
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;
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; GFX11-LABEL: s_mad_u16:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_mul_i32 s0, s0, s1
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; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GFX11-NEXT: s_add_i32 s0, s0, s2
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; GFX11-NEXT: ; return to shader part epilog
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%mul = mul i16 %arg0, %arg1
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%add = add i16 %mul, %arg2
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ret i16 %add
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}
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define amdgpu_ps i32 @s_mad_u16_zext(i16 inreg %arg0, i16 inreg %arg1, i16 inreg %arg2) {
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; GFX8-LABEL: s_mad_u16_zext:
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; GFX8: ; %bb.0:
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; GFX8-NEXT: s_mul_i32 s0, s0, s1
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; GFX8-NEXT: s_add_i32 s0, s0, s2
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; GFX8-NEXT: s_and_b32 s0, s0, 0xffff
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; GFX8-NEXT: ; return to shader part epilog
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;
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; GFX9-LABEL: s_mad_u16_zext:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_mul_i32 s0, s0, s1
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; GFX9-NEXT: s_add_i32 s0, s0, s2
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; GFX9-NEXT: s_and_b32 s0, s0, 0xffff
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: s_mad_u16_zext:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_mul_i32 s0, s0, s1
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; GFX10-NEXT: s_add_i32 s0, s0, s2
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; GFX10-NEXT: s_and_b32 s0, s0, 0xffff
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; GFX10-NEXT: ; return to shader part epilog
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;
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; GFX11-LABEL: s_mad_u16_zext:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_mul_i32 s0, s0, s1
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; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
|
||
|
|
; GFX11-NEXT: s_add_i32 s0, s0, s2
|
||
|
|
; GFX11-NEXT: s_and_b32 s0, s0, 0xffff
|
||
|
|
; GFX11-NEXT: ; return to shader part epilog
|
||
|
|
%mul = mul i16 %arg0, %arg1
|
||
|
|
%add = add i16 %mul, %arg2
|
||
|
|
%zext = zext i16 %add to i32
|
||
|
|
ret i32 %zext
|
||
|
|
}
|
||
|
|
|
||
|
|
define amdgpu_ps i64 @s_mad_u16_zext64(i16 inreg %arg0, i16 inreg %arg1, i16 inreg %arg2) {
|
||
|
|
; GFX8-LABEL: s_mad_u16_zext64:
|
||
|
|
; GFX8: ; %bb.0:
|
||
|
|
; GFX8-NEXT: s_mul_i32 s0, s0, s1
|
||
|
|
; GFX8-NEXT: s_add_i32 s0, s0, s2
|
||
|
|
; GFX8-NEXT: s_and_b32 s0, s0, 0xffff
|
||
|
|
; GFX8-NEXT: s_mov_b32 s1, 0
|
||
|
|
; GFX8-NEXT: ; return to shader part epilog
|
||
|
|
;
|
||
|
|
; GFX9-LABEL: s_mad_u16_zext64:
|
||
|
|
; GFX9: ; %bb.0:
|
||
|
|
; GFX9-NEXT: s_mul_i32 s0, s0, s1
|
||
|
|
; GFX9-NEXT: s_add_i32 s0, s0, s2
|
||
|
|
; GFX9-NEXT: s_and_b32 s0, s0, 0xffff
|
||
|
|
; GFX9-NEXT: s_mov_b32 s1, 0
|
||
|
|
; GFX9-NEXT: ; return to shader part epilog
|
||
|
|
;
|
||
|
|
; GFX10-LABEL: s_mad_u16_zext64:
|
||
|
|
; GFX10: ; %bb.0:
|
||
|
|
; GFX10-NEXT: s_mul_i32 s0, s0, s1
|
||
|
|
; GFX10-NEXT: s_mov_b32 s1, 0
|
||
|
|
; GFX10-NEXT: s_add_i32 s0, s0, s2
|
||
|
|
; GFX10-NEXT: s_and_b32 s0, s0, 0xffff
|
||
|
|
; GFX10-NEXT: ; return to shader part epilog
|
||
|
|
;
|
||
|
|
; GFX11-LABEL: s_mad_u16_zext64:
|
||
|
|
; GFX11: ; %bb.0:
|
||
|
|
; GFX11-NEXT: s_mul_i32 s0, s0, s1
|
||
|
|
; GFX11-NEXT: s_mov_b32 s1, 0
|
||
|
|
; GFX11-NEXT: s_add_i32 s0, s0, s2
|
||
|
|
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
||
|
|
; GFX11-NEXT: s_and_b32 s0, s0, 0xffff
|
||
|
|
; GFX11-NEXT: ; return to shader part epilog
|
||
|
|
%mul = mul i16 %arg0, %arg1
|
||
|
|
%add = add i16 %mul, %arg2
|
||
|
|
%zext = zext i16 %add to i64
|
||
|
|
ret i64 %zext
|
||
|
|
}
|
||
|
|
|
||
|
|
define amdgpu_ps i32 @s_mad_u16_sext(i16 inreg %arg0, i16 inreg %arg1, i16 inreg %arg2) {
|
||
|
|
; GFX8-LABEL: s_mad_u16_sext:
|
||
|
|
; GFX8: ; %bb.0:
|
||
|
|
; GFX8-NEXT: s_mul_i32 s0, s0, s1
|
||
|
|
; GFX8-NEXT: s_add_i32 s0, s0, s2
|
||
|
|
; GFX8-NEXT: s_sext_i32_i16 s0, s0
|
||
|
|
; GFX8-NEXT: ; return to shader part epilog
|
||
|
|
;
|
||
|
|
; GFX9-LABEL: s_mad_u16_sext:
|
||
|
|
; GFX9: ; %bb.0:
|
||
|
|
; GFX9-NEXT: s_mul_i32 s0, s0, s1
|
||
|
|
; GFX9-NEXT: s_add_i32 s0, s0, s2
|
||
|
|
; GFX9-NEXT: s_sext_i32_i16 s0, s0
|
||
|
|
; GFX9-NEXT: ; return to shader part epilog
|
||
|
|
;
|
||
|
|
; GFX10-LABEL: s_mad_u16_sext:
|
||
|
|
; GFX10: ; %bb.0:
|
||
|
|
; GFX10-NEXT: s_mul_i32 s0, s0, s1
|
||
|
|
; GFX10-NEXT: s_add_i32 s0, s0, s2
|
||
|
|
; GFX10-NEXT: s_sext_i32_i16 s0, s0
|
||
|
|
; GFX10-NEXT: ; return to shader part epilog
|
||
|
|
;
|
||
|
|
; GFX11-LABEL: s_mad_u16_sext:
|
||
|
|
; GFX11: ; %bb.0:
|
||
|
|
; GFX11-NEXT: s_mul_i32 s0, s0, s1
|
||
|
|
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
|
||
|
|
; GFX11-NEXT: s_add_i32 s0, s0, s2
|
||
|
|
; GFX11-NEXT: s_sext_i32_i16 s0, s0
|
||
|
|
; GFX11-NEXT: ; return to shader part epilog
|
||
|
|
%mul = mul i16 %arg0, %arg1
|
||
|
|
%add = add i16 %mul, %arg2
|
||
|
|
%sext = sext i16 %add to i32
|
||
|
|
ret i32 %sext
|
||
|
|
}
|
||
|
|
|
||
|
|
declare i32 @llvm.amdgcn.workitem.id.x()
|
||
|
|
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
|
||
|
|
; GCN: {{.*}}
|