45 lines
1.7 KiB
LLVM
45 lines
1.7 KiB
LLVM
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; RUN: llc -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; --------------------------------------------------------------------------------
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; Don't fold if fneg can fold into the source
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; --------------------------------------------------------------------------------
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; GCN-LABEL: {{^}}select_fneg_posk_src_rcp_legacy_f32:
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; GCN: buffer_load_dword [[X:v[0-9]+]]
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; GCN: v_rcp_legacy_f32_e64 [[RCP:v[0-9]+]], -[[X]]
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; GCN: v_cndmask_b32_e32 [[SELECT:v[0-9]+]], 2.0, [[RCP]], vcc
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; GCN-NEXT: buffer_store_dword [[SELECT]]
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define amdgpu_kernel void @select_fneg_posk_src_rcp_legacy_f32(i32 %c) #2 {
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%x = load volatile float, ptr addrspace(1) undef
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%y = load volatile float, ptr addrspace(1) undef
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%cmp = icmp eq i32 %c, 0
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%rcp = call float @llvm.amdgcn.rcp.legacy(float %x)
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%fneg = fsub float -0.0, %rcp
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%select = select i1 %cmp, float %fneg, float 2.0
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store volatile float %select, ptr addrspace(1) undef
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ret void
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}
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; GCN-LABEL: {{^}}select_fneg_posk_src_mul_legacy_f32:
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; GCN: buffer_load_dword [[X:v[0-9]+]]
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; GCN: v_mul_legacy_f32_e32 [[MUL:v[0-9]+]], -4.0, [[X]]
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; GCN: v_cndmask_b32_e32 [[SELECT:v[0-9]+]], 2.0, [[MUL]], vcc
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; GCN-NEXT: buffer_store_dword [[SELECT]]
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define amdgpu_kernel void @select_fneg_posk_src_mul_legacy_f32(i32 %c) #2 {
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%x = load volatile float, ptr addrspace(1) undef
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%cmp = icmp eq i32 %c, 0
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%mul = call float @llvm.amdgcn.fmul.legacy(float %x, float 4.0)
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%fneg = fsub float -0.0, %mul
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%select = select i1 %cmp, float %fneg, float 2.0
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store volatile float %select, ptr addrspace(1) undef
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ret void
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}
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declare float @llvm.amdgcn.rcp.legacy(float) #1
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declare float @llvm.amdgcn.fmul.legacy(float, float) #1
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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