53 lines
1.5 KiB
LLVM
53 lines
1.5 KiB
LLVM
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; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,WAVE64 %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,WAVE32 %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,WAVE32 %s
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; GCN-LABEL: {{^}}sub_var_var_i1:
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; WAVE32: s_xor_b32
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; WAVE64: s_xor_b64
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define amdgpu_kernel void @sub_var_var_i1(ptr addrspace(1) %out, ptr addrspace(1) %in0, ptr addrspace(1) %in1) {
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%a = load volatile i1, ptr addrspace(1) %in0
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%b = load volatile i1, ptr addrspace(1) %in1
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%sub = sub i1 %a, %b
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store i1 %sub, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}sub_var_imm_i1:
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; WAVE32: s_not_b32
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; WAVE64: s_not_b64
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define amdgpu_kernel void @sub_var_imm_i1(ptr addrspace(1) %out, ptr addrspace(1) %in) {
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%a = load volatile i1, ptr addrspace(1) %in
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%sub = sub i1 %a, 1
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store i1 %sub, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}sub_i1_cf:
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; GCN: ; %endif
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; WAVE32: s_not_b32
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; WAVE64: s_not_b64
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define amdgpu_kernel void @sub_i1_cf(ptr addrspace(1) %out, ptr addrspace(1) %a, ptr addrspace(1) %b) {
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entry:
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%d_cmp = icmp ult i32 %tid, 16
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br i1 %d_cmp, label %if, label %else
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if:
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%0 = load volatile i1, ptr addrspace(1) %a
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br label %endif
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else:
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%1 = load volatile i1, ptr addrspace(1) %b
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br label %endif
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endif:
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%2 = phi i1 [%0, %if], [%1, %else]
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%3 = sub i1 %2, -1
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store i1 %3, ptr addrspace(1) %out
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x()
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