99 lines
3.2 KiB
LLVM
99 lines
3.2 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
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declare <32 x i8> @llvm.loongarch.lasx.xvavgr.b(<32 x i8>, <32 x i8>)
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define <32 x i8> @lasx_xvavgr_b(<32 x i8> %va, <32 x i8> %vb) nounwind {
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; CHECK-LABEL: lasx_xvavgr_b:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvavgr.b $xr0, $xr0, $xr1
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; CHECK-NEXT: ret
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entry:
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%res = call <32 x i8> @llvm.loongarch.lasx.xvavgr.b(<32 x i8> %va, <32 x i8> %vb)
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ret <32 x i8> %res
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}
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declare <16 x i16> @llvm.loongarch.lasx.xvavgr.h(<16 x i16>, <16 x i16>)
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define <16 x i16> @lasx_xvavgr_h(<16 x i16> %va, <16 x i16> %vb) nounwind {
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; CHECK-LABEL: lasx_xvavgr_h:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvavgr.h $xr0, $xr0, $xr1
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; CHECK-NEXT: ret
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entry:
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%res = call <16 x i16> @llvm.loongarch.lasx.xvavgr.h(<16 x i16> %va, <16 x i16> %vb)
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ret <16 x i16> %res
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}
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declare <8 x i32> @llvm.loongarch.lasx.xvavgr.w(<8 x i32>, <8 x i32>)
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define <8 x i32> @lasx_xvavgr_w(<8 x i32> %va, <8 x i32> %vb) nounwind {
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; CHECK-LABEL: lasx_xvavgr_w:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvavgr.w $xr0, $xr0, $xr1
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; CHECK-NEXT: ret
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entry:
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%res = call <8 x i32> @llvm.loongarch.lasx.xvavgr.w(<8 x i32> %va, <8 x i32> %vb)
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ret <8 x i32> %res
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}
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declare <4 x i64> @llvm.loongarch.lasx.xvavgr.d(<4 x i64>, <4 x i64>)
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define <4 x i64> @lasx_xvavgr_d(<4 x i64> %va, <4 x i64> %vb) nounwind {
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; CHECK-LABEL: lasx_xvavgr_d:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvavgr.d $xr0, $xr0, $xr1
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; CHECK-NEXT: ret
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entry:
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%res = call <4 x i64> @llvm.loongarch.lasx.xvavgr.d(<4 x i64> %va, <4 x i64> %vb)
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ret <4 x i64> %res
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}
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declare <32 x i8> @llvm.loongarch.lasx.xvavgr.bu(<32 x i8>, <32 x i8>)
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define <32 x i8> @lasx_xvavgr_bu(<32 x i8> %va, <32 x i8> %vb) nounwind {
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; CHECK-LABEL: lasx_xvavgr_bu:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvavgr.bu $xr0, $xr0, $xr1
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; CHECK-NEXT: ret
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entry:
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%res = call <32 x i8> @llvm.loongarch.lasx.xvavgr.bu(<32 x i8> %va, <32 x i8> %vb)
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ret <32 x i8> %res
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}
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declare <16 x i16> @llvm.loongarch.lasx.xvavgr.hu(<16 x i16>, <16 x i16>)
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define <16 x i16> @lasx_xvavgr_hu(<16 x i16> %va, <16 x i16> %vb) nounwind {
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; CHECK-LABEL: lasx_xvavgr_hu:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvavgr.hu $xr0, $xr0, $xr1
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; CHECK-NEXT: ret
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entry:
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%res = call <16 x i16> @llvm.loongarch.lasx.xvavgr.hu(<16 x i16> %va, <16 x i16> %vb)
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ret <16 x i16> %res
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}
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declare <8 x i32> @llvm.loongarch.lasx.xvavgr.wu(<8 x i32>, <8 x i32>)
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define <8 x i32> @lasx_xvavgr_wu(<8 x i32> %va, <8 x i32> %vb) nounwind {
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; CHECK-LABEL: lasx_xvavgr_wu:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvavgr.wu $xr0, $xr0, $xr1
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; CHECK-NEXT: ret
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entry:
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%res = call <8 x i32> @llvm.loongarch.lasx.xvavgr.wu(<8 x i32> %va, <8 x i32> %vb)
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ret <8 x i32> %res
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}
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declare <4 x i64> @llvm.loongarch.lasx.xvavgr.du(<4 x i64>, <4 x i64>)
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define <4 x i64> @lasx_xvavgr_du(<4 x i64> %va, <4 x i64> %vb) nounwind {
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; CHECK-LABEL: lasx_xvavgr_du:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvavgr.du $xr0, $xr0, $xr1
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; CHECK-NEXT: ret
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entry:
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%res = call <4 x i64> @llvm.loongarch.lasx.xvavgr.du(<4 x i64> %va, <4 x i64> %vb)
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ret <4 x i64> %res
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}
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