99 lines
3.1 KiB
LLVM
99 lines
3.1 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
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declare <32 x i8> @llvm.loongarch.lasx.xvbitclr.b(<32 x i8>, <32 x i8>)
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define <32 x i8> @lasx_xvbitclr_b(<32 x i8> %va, <32 x i8> %vb) nounwind {
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; CHECK-LABEL: lasx_xvbitclr_b:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvbitclr.b $xr0, $xr0, $xr1
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; CHECK-NEXT: ret
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entry:
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%res = call <32 x i8> @llvm.loongarch.lasx.xvbitclr.b(<32 x i8> %va, <32 x i8> %vb)
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ret <32 x i8> %res
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}
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declare <16 x i16> @llvm.loongarch.lasx.xvbitclr.h(<16 x i16>, <16 x i16>)
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define <16 x i16> @lasx_xvbitclr_h(<16 x i16> %va, <16 x i16> %vb) nounwind {
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; CHECK-LABEL: lasx_xvbitclr_h:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvbitclr.h $xr0, $xr0, $xr1
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; CHECK-NEXT: ret
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entry:
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%res = call <16 x i16> @llvm.loongarch.lasx.xvbitclr.h(<16 x i16> %va, <16 x i16> %vb)
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ret <16 x i16> %res
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}
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declare <8 x i32> @llvm.loongarch.lasx.xvbitclr.w(<8 x i32>, <8 x i32>)
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define <8 x i32> @lasx_xvbitclr_w(<8 x i32> %va, <8 x i32> %vb) nounwind {
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; CHECK-LABEL: lasx_xvbitclr_w:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvbitclr.w $xr0, $xr0, $xr1
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; CHECK-NEXT: ret
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entry:
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%res = call <8 x i32> @llvm.loongarch.lasx.xvbitclr.w(<8 x i32> %va, <8 x i32> %vb)
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ret <8 x i32> %res
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}
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declare <4 x i64> @llvm.loongarch.lasx.xvbitclr.d(<4 x i64>, <4 x i64>)
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define <4 x i64> @lasx_xvbitclr_d(<4 x i64> %va, <4 x i64> %vb) nounwind {
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; CHECK-LABEL: lasx_xvbitclr_d:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvbitclr.d $xr0, $xr0, $xr1
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; CHECK-NEXT: ret
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entry:
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%res = call <4 x i64> @llvm.loongarch.lasx.xvbitclr.d(<4 x i64> %va, <4 x i64> %vb)
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ret <4 x i64> %res
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}
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declare <32 x i8> @llvm.loongarch.lasx.xvbitclri.b(<32 x i8>, i32)
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define <32 x i8> @lasx_xvbitclri_b(<32 x i8> %va) nounwind {
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; CHECK-LABEL: lasx_xvbitclri_b:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvbitclri.b $xr0, $xr0, 1
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; CHECK-NEXT: ret
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entry:
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%res = call <32 x i8> @llvm.loongarch.lasx.xvbitclri.b(<32 x i8> %va, i32 1)
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ret <32 x i8> %res
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}
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declare <16 x i16> @llvm.loongarch.lasx.xvbitclri.h(<16 x i16>, i32)
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define <16 x i16> @lasx_xvbitclri_h(<16 x i16> %va) nounwind {
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; CHECK-LABEL: lasx_xvbitclri_h:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvbitclri.h $xr0, $xr0, 1
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; CHECK-NEXT: ret
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entry:
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%res = call <16 x i16> @llvm.loongarch.lasx.xvbitclri.h(<16 x i16> %va, i32 1)
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ret <16 x i16> %res
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}
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declare <8 x i32> @llvm.loongarch.lasx.xvbitclri.w(<8 x i32>, i32)
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define <8 x i32> @lasx_xvbitclri_w(<8 x i32> %va) nounwind {
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; CHECK-LABEL: lasx_xvbitclri_w:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvbitclri.w $xr0, $xr0, 1
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; CHECK-NEXT: ret
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entry:
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%res = call <8 x i32> @llvm.loongarch.lasx.xvbitclri.w(<8 x i32> %va, i32 1)
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ret <8 x i32> %res
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}
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declare <4 x i64> @llvm.loongarch.lasx.xvbitclri.d(<4 x i64>, i32)
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define <4 x i64> @lasx_xvbitclri_d(<4 x i64> %va) nounwind {
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; CHECK-LABEL: lasx_xvbitclri_d:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvbitclri.d $xr0, $xr0, 1
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; CHECK-NEXT: ret
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entry:
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%res = call <4 x i64> @llvm.loongarch.lasx.xvbitclri.d(<4 x i64> %va, i32 1)
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ret <4 x i64> %res
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}
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