99 lines
3.1 KiB
LLVM
99 lines
3.1 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
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declare <16 x i8> @llvm.loongarch.lsx.vavg.b(<16 x i8>, <16 x i8>)
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define <16 x i8> @lsx_vavg_b(<16 x i8> %va, <16 x i8> %vb) nounwind {
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; CHECK-LABEL: lsx_vavg_b:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vavg.b $vr0, $vr0, $vr1
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; CHECK-NEXT: ret
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entry:
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%res = call <16 x i8> @llvm.loongarch.lsx.vavg.b(<16 x i8> %va, <16 x i8> %vb)
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ret <16 x i8> %res
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}
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declare <8 x i16> @llvm.loongarch.lsx.vavg.h(<8 x i16>, <8 x i16>)
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define <8 x i16> @lsx_vavg_h(<8 x i16> %va, <8 x i16> %vb) nounwind {
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; CHECK-LABEL: lsx_vavg_h:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vavg.h $vr0, $vr0, $vr1
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; CHECK-NEXT: ret
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entry:
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%res = call <8 x i16> @llvm.loongarch.lsx.vavg.h(<8 x i16> %va, <8 x i16> %vb)
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ret <8 x i16> %res
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}
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declare <4 x i32> @llvm.loongarch.lsx.vavg.w(<4 x i32>, <4 x i32>)
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define <4 x i32> @lsx_vavg_w(<4 x i32> %va, <4 x i32> %vb) nounwind {
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; CHECK-LABEL: lsx_vavg_w:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vavg.w $vr0, $vr0, $vr1
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; CHECK-NEXT: ret
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entry:
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%res = call <4 x i32> @llvm.loongarch.lsx.vavg.w(<4 x i32> %va, <4 x i32> %vb)
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ret <4 x i32> %res
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}
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declare <2 x i64> @llvm.loongarch.lsx.vavg.d(<2 x i64>, <2 x i64>)
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define <2 x i64> @lsx_vavg_d(<2 x i64> %va, <2 x i64> %vb) nounwind {
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; CHECK-LABEL: lsx_vavg_d:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vavg.d $vr0, $vr0, $vr1
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; CHECK-NEXT: ret
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entry:
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%res = call <2 x i64> @llvm.loongarch.lsx.vavg.d(<2 x i64> %va, <2 x i64> %vb)
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ret <2 x i64> %res
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}
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declare <16 x i8> @llvm.loongarch.lsx.vavg.bu(<16 x i8>, <16 x i8>)
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define <16 x i8> @lsx_vavg_bu(<16 x i8> %va, <16 x i8> %vb) nounwind {
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; CHECK-LABEL: lsx_vavg_bu:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vavg.bu $vr0, $vr0, $vr1
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; CHECK-NEXT: ret
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entry:
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%res = call <16 x i8> @llvm.loongarch.lsx.vavg.bu(<16 x i8> %va, <16 x i8> %vb)
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ret <16 x i8> %res
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}
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declare <8 x i16> @llvm.loongarch.lsx.vavg.hu(<8 x i16>, <8 x i16>)
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define <8 x i16> @lsx_vavg_hu(<8 x i16> %va, <8 x i16> %vb) nounwind {
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; CHECK-LABEL: lsx_vavg_hu:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vavg.hu $vr0, $vr0, $vr1
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; CHECK-NEXT: ret
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entry:
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%res = call <8 x i16> @llvm.loongarch.lsx.vavg.hu(<8 x i16> %va, <8 x i16> %vb)
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ret <8 x i16> %res
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}
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declare <4 x i32> @llvm.loongarch.lsx.vavg.wu(<4 x i32>, <4 x i32>)
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define <4 x i32> @lsx_vavg_wu(<4 x i32> %va, <4 x i32> %vb) nounwind {
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; CHECK-LABEL: lsx_vavg_wu:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vavg.wu $vr0, $vr0, $vr1
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; CHECK-NEXT: ret
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entry:
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%res = call <4 x i32> @llvm.loongarch.lsx.vavg.wu(<4 x i32> %va, <4 x i32> %vb)
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ret <4 x i32> %res
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}
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declare <2 x i64> @llvm.loongarch.lsx.vavg.du(<2 x i64>, <2 x i64>)
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define <2 x i64> @lsx_vavg_du(<2 x i64> %va, <2 x i64> %vb) nounwind {
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; CHECK-LABEL: lsx_vavg_du:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vavg.du $vr0, $vr0, $vr1
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; CHECK-NEXT: ret
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entry:
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%res = call <2 x i64> @llvm.loongarch.lsx.vavg.du(<2 x i64> %va, <2 x i64> %vb)
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ret <2 x i64> %res
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}
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