75 lines
2.3 KiB
LLVM
75 lines
2.3 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
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declare <8 x i16> @llvm.loongarch.lsx.vsllwil.h.b(<16 x i8>, i32)
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define <8 x i16> @lsx_vsllwil_h_b(<16 x i8> %va) nounwind {
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; CHECK-LABEL: lsx_vsllwil_h_b:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsllwil.h.b $vr0, $vr0, 1
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; CHECK-NEXT: ret
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entry:
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%res = call <8 x i16> @llvm.loongarch.lsx.vsllwil.h.b(<16 x i8> %va, i32 1)
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ret <8 x i16> %res
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}
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declare <4 x i32> @llvm.loongarch.lsx.vsllwil.w.h(<8 x i16>, i32)
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define <4 x i32> @lsx_vsllwil_w_h(<8 x i16> %va) nounwind {
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; CHECK-LABEL: lsx_vsllwil_w_h:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsllwil.w.h $vr0, $vr0, 1
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; CHECK-NEXT: ret
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entry:
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%res = call <4 x i32> @llvm.loongarch.lsx.vsllwil.w.h(<8 x i16> %va, i32 1)
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ret <4 x i32> %res
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}
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declare <2 x i64> @llvm.loongarch.lsx.vsllwil.d.w(<4 x i32>, i32)
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define <2 x i64> @lsx_vsllwil_d_w(<4 x i32> %va) nounwind {
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; CHECK-LABEL: lsx_vsllwil_d_w:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsllwil.d.w $vr0, $vr0, 1
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; CHECK-NEXT: ret
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entry:
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%res = call <2 x i64> @llvm.loongarch.lsx.vsllwil.d.w(<4 x i32> %va, i32 1)
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ret <2 x i64> %res
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}
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declare <8 x i16> @llvm.loongarch.lsx.vsllwil.hu.bu(<16 x i8>, i32)
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define <8 x i16> @lsx_vsllwil_hu_bu(<16 x i8> %va) nounwind {
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; CHECK-LABEL: lsx_vsllwil_hu_bu:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsllwil.hu.bu $vr0, $vr0, 7
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; CHECK-NEXT: ret
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entry:
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%res = call <8 x i16> @llvm.loongarch.lsx.vsllwil.hu.bu(<16 x i8> %va, i32 7)
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ret <8 x i16> %res
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}
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declare <4 x i32> @llvm.loongarch.lsx.vsllwil.wu.hu(<8 x i16>, i32)
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define <4 x i32> @lsx_vsllwil_wu_hu(<8 x i16> %va) nounwind {
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; CHECK-LABEL: lsx_vsllwil_wu_hu:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsllwil.wu.hu $vr0, $vr0, 15
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; CHECK-NEXT: ret
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entry:
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%res = call <4 x i32> @llvm.loongarch.lsx.vsllwil.wu.hu(<8 x i16> %va, i32 15)
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ret <4 x i32> %res
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}
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declare <2 x i64> @llvm.loongarch.lsx.vsllwil.du.wu(<4 x i32>, i32)
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define <2 x i64> @lsx_vsllwil_du_wu(<4 x i32> %va) nounwind {
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; CHECK-LABEL: lsx_vsllwil_du_wu:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsllwil.du.wu $vr0, $vr0, 31
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; CHECK-NEXT: ret
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entry:
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%res = call <2 x i64> @llvm.loongarch.lsx.vsllwil.du.wu(<4 x i32> %va, i32 31)
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ret <2 x i64> %res
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}
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