135 lines
3.9 KiB
LLVM
135 lines
3.9 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
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define void @sdiv_v16i8(ptr %res, ptr %a0, ptr %a1) nounwind {
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; CHECK-LABEL: sdiv_v16i8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a2, 0
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; CHECK-NEXT: vld $vr1, $a1, 0
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; CHECK-NEXT: vdiv.b $vr0, $vr1, $vr0
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <16 x i8>, ptr %a0
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%v1 = load <16 x i8>, ptr %a1
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%v2 = sdiv <16 x i8> %v0, %v1
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store <16 x i8> %v2, ptr %res
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ret void
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}
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define void @sdiv_v8i16(ptr %res, ptr %a0, ptr %a1) nounwind {
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; CHECK-LABEL: sdiv_v8i16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a2, 0
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; CHECK-NEXT: vld $vr1, $a1, 0
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; CHECK-NEXT: vdiv.h $vr0, $vr1, $vr0
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <8 x i16>, ptr %a0
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%v1 = load <8 x i16>, ptr %a1
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%v2 = sdiv <8 x i16> %v0, %v1
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store <8 x i16> %v2, ptr %res
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ret void
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}
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define void @sdiv_v4i32(ptr %res, ptr %a0, ptr %a1) nounwind {
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; CHECK-LABEL: sdiv_v4i32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a2, 0
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; CHECK-NEXT: vld $vr1, $a1, 0
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; CHECK-NEXT: vdiv.w $vr0, $vr1, $vr0
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <4 x i32>, ptr %a0
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%v1 = load <4 x i32>, ptr %a1
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%v2 = sdiv <4 x i32> %v0, %v1
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store <4 x i32> %v2, ptr %res
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ret void
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}
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define void @sdiv_v2i64(ptr %res, ptr %a0, ptr %a1) nounwind {
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; CHECK-LABEL: sdiv_v2i64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a2, 0
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; CHECK-NEXT: vld $vr1, $a1, 0
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; CHECK-NEXT: vdiv.d $vr0, $vr1, $vr0
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <2 x i64>, ptr %a0
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%v1 = load <2 x i64>, ptr %a1
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%v2 = sdiv <2 x i64> %v0, %v1
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store <2 x i64> %v2, ptr %res
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ret void
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}
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define void @sdiv_v16i8_8(ptr %res, ptr %a0) nounwind {
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; CHECK-LABEL: sdiv_v16i8_8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a1, 0
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; CHECK-NEXT: vsrai.b $vr1, $vr0, 7
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; CHECK-NEXT: vsrli.b $vr1, $vr1, 5
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; CHECK-NEXT: vadd.b $vr0, $vr0, $vr1
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; CHECK-NEXT: vsrai.b $vr0, $vr0, 3
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <16 x i8>, ptr %a0
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%v1 = sdiv <16 x i8> %v0, <i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8>
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store <16 x i8> %v1, ptr %res
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ret void
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}
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define void @sdiv_v8i16_8(ptr %res, ptr %a0) nounwind {
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; CHECK-LABEL: sdiv_v8i16_8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a1, 0
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; CHECK-NEXT: vsrai.h $vr1, $vr0, 15
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; CHECK-NEXT: vsrli.h $vr1, $vr1, 13
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; CHECK-NEXT: vadd.h $vr0, $vr0, $vr1
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; CHECK-NEXT: vsrai.h $vr0, $vr0, 3
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <8 x i16>, ptr %a0
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%v1 = sdiv <8 x i16> %v0, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
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store <8 x i16> %v1, ptr %res
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ret void
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}
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define void @sdiv_v4i32_8(ptr %res, ptr %a0) nounwind {
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; CHECK-LABEL: sdiv_v4i32_8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a1, 0
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; CHECK-NEXT: vsrai.w $vr1, $vr0, 31
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; CHECK-NEXT: vsrli.w $vr1, $vr1, 29
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; CHECK-NEXT: vadd.w $vr0, $vr0, $vr1
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; CHECK-NEXT: vsrai.w $vr0, $vr0, 3
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <4 x i32>, ptr %a0
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%v1 = sdiv <4 x i32> %v0, <i32 8, i32 8, i32 8, i32 8>
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store <4 x i32> %v1, ptr %res
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ret void
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}
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define void @sdiv_v2i64_8(ptr %res, ptr %a0) nounwind {
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; CHECK-LABEL: sdiv_v2i64_8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a1, 0
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; CHECK-NEXT: vsrai.d $vr1, $vr0, 63
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; CHECK-NEXT: vsrli.d $vr1, $vr1, 61
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; CHECK-NEXT: vadd.d $vr0, $vr0, $vr1
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; CHECK-NEXT: vsrai.d $vr0, $vr0, 3
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <2 x i64>, ptr %a0
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%v1 = sdiv <2 x i64> %v0, <i64 8, i64 8>
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store <2 x i64> %v1, ptr %res
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ret void
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}
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