311 lines
12 KiB
LLVM
311 lines
12 KiB
LLVM
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; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \
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; RUN: -xcoff-traceback-table=false --code-model=large -filetype=obj -o %t.o < %s
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; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck --check-prefix=RELOC %s
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; RUN: llvm-readobj --syms %t.o | FileCheck --check-prefix=SYM %s
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; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck --check-prefix=DIS %s
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@ThreadLocalVarInit = thread_local(localexec) global i64 1, align 8
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@VarInit = global i64 87, align 8
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@IThreadLocalVarUninit = internal thread_local(localexec) global i64 0, align 8
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@IThreadLocalVarUninit2 = internal thread_local(localexec) global i64 0, align 8
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declare nonnull ptr @llvm.threadlocal.address.p0(ptr nonnull)
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define void @storeITLUninit(i64 noundef %x) {
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entry:
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%0 = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @IThreadLocalVarUninit)
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store i64 %x, ptr %0, align 8
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ret void
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}
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define i64 @loadTLInit() {
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entry:
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%0 = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @ThreadLocalVarInit)
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%1 = load i64, ptr %0, align 8
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%2 = load i64, ptr @VarInit, align 8
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%add = add nsw i64 %2, %1
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ret i64 %add
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}
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define signext i64 @loadTLUninit() {
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entry:
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%0 = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @IThreadLocalVarUninit)
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store i64 1, ptr %0, align 8
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%1 = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @IThreadLocalVarUninit2)
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%2 = load i64, ptr %1, align 8
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%add = add nsw i64 %2, 1
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ret i64 %add
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}
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; RELOC: File: {{.*}}aix-tls-le-xcoff-reloc-large.ll.tmp.o
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; RELOC-NEXT: Format: aix5coff64-rs6000
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; RELOC-NEXT: Arch: powerpc64
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; RELOC-NEXT: AddressSize: 64bit
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; RELOC-NEXT: Relocations [
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; RELOC: Virtual Address: 0x2
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; RELOC-NEXT: Symbol: IThreadLocalVarUninit (19)
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; RELOC-NEXT: IsSigned: No
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; RELOC-NEXT: FixupBitValue: 0
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; RELOC-NEXT: Length: 16
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; RELOC-NEXT: Type: R_TOCU (0x30)
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; RELOC-NEXT: }
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; RELOC: Virtual Address: 0x6
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; RELOC-NEXT: Symbol: IThreadLocalVarUninit (19)
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; RELOC-NEXT: IsSigned: No
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; RELOC-NEXT: FixupBitValue: 0
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; RELOC-NEXT: Length: 16
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; RELOC-NEXT: Type: R_TOCL (0x31)
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; RELOC-NEXT: }
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; RELOC: Virtual Address: 0x12
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; RELOC-NEXT: Symbol: ThreadLocalVarInit (21)
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; RELOC-NEXT: IsSigned: No
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; RELOC-NEXT: FixupBitValue: 0
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; RELOC-NEXT: Length: 16
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; RELOC-NEXT: Type: R_TOCU (0x30)
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; RELOC-NEXT: }
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; RELOC: Virtual Address: 0x1A
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; RELOC-NEXT: Symbol: ThreadLocalVarInit (21)
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; RELOC-NEXT: IsSigned: No
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; RELOC-NEXT: FixupBitValue: 0
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; RELOC-NEXT: Length: 16
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; RELOC-NEXT: Type: R_TOCL (0x31)
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; RELOC-NEXT: }
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; RELOC: Virtual Address: 0x42
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; RELOC-NEXT: Symbol: IThreadLocalVarUninit2 (25)
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; RELOC-NEXT: IsSigned: No
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; RELOC-NEXT: FixupBitValue: 0
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; RELOC-NEXT: Length: 16
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; RELOC-NEXT: Type: R_TOCU (0x30)
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; RELOC-NEXT: }
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; RELOC: Virtual Address: 0x46
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; RELOC-NEXT: Symbol: IThreadLocalVarUninit2 (25)
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; RELOC-NEXT: IsSigned: No
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; RELOC-NEXT: FixupBitValue: 0
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; RELOC-NEXT: Length: 16
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; RELOC-NEXT: Type: R_TOCL (0x31)
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; RELOC-NEXT: }
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; RELOC: Virtual Address: 0xA8
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; RELOC-NEXT: Symbol: IThreadLocalVarUninit (29)
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; RELOC-NEXT: IsSigned: No
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; RELOC-NEXT: FixupBitValue: 0
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; RELOC-NEXT: Length: 64
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; RELOC-NEXT: Type: R_TLS_LE (0x23)
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; RELOC-NEXT: }
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; RELOC: Virtual Address: 0xB0
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; RELOC-NEXT: Symbol: ThreadLocalVarInit (27)
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; RELOC-NEXT: IsSigned: No
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; RELOC-NEXT: FixupBitValue: 0
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; RELOC-NEXT: Length: 64
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; RELOC-NEXT: Type: R_TLS_LE (0x23)
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; RELOC-NEXT: }
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; RELOC: Virtual Address: 0xC0
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; RELOC-NEXT: Symbol: IThreadLocalVarUninit2 (31)
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; RELOC-NEXT: IsSigned: No
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; RELOC-NEXT: FixupBitValue: 0
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; RELOC-NEXT: Length: 64
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; RELOC-NEXT: Type: R_TLS_LE (0x23)
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; RELOC-NEXT: }
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; SYM: File: {{.*}}aix-tls-le-xcoff-reloc-large.ll.tmp.o
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; SYM-NEXT: Format: aix5coff64-rs6000
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; SYM-NEXT: Arch: powerpc64
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; SYM-NEXT: AddressSize: 64bit
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; SYM-NEXT: Symbols [
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; SYM: Index: 19
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; SYM-NEXT: Name: IThreadLocalVarUninit
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; SYM-NEXT: Value (RelocatableAddress): 0xA8
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; SYM-NEXT: Section: .data
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; SYM-NEXT: Type: 0x0
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; SYM-NEXT: StorageClass: C_HIDEXT (0x6B)
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; SYM-NEXT: NumberOfAuxEntries: 1
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; SYM-NEXT: CSECT Auxiliary Entry {
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; SYM-NEXT: Index: 20
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; SYM-NEXT: SectionLen: 8
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; SYM-NEXT: ParameterHashIndex: 0x0
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; SYM-NEXT: TypeChkSectNum: 0x0
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; SYM-NEXT: SymbolAlignmentLog2: 3
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; SYM-NEXT: SymbolType: XTY_SD (0x1)
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; SYM-NEXT: StorageMappingClass: XMC_TE (0x16)
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; SYM-NEXT: Auxiliary Type: AUX_CSECT (0xFB)
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; SYM-NEXT: }
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; SYM-NEXT: }
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; SYM: Index: 21
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; SYM-NEXT: Name: ThreadLocalVarInit
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; SYM-NEXT: Value (RelocatableAddress): 0xB0
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; SYM-NEXT: Section: .data
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; SYM-NEXT: Type: 0x0
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; SYM-NEXT: StorageClass: C_HIDEXT (0x6B)
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; SYM-NEXT: NumberOfAuxEntries: 1
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; SYM-NEXT: CSECT Auxiliary Entry {
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; SYM-NEXT: Index: 22
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; SYM-NEXT: SectionLen: 8
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; SYM-NEXT: ParameterHashIndex: 0x0
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; SYM-NEXT: TypeChkSectNum: 0x0
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; SYM-NEXT: SymbolAlignmentLog2: 3
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; SYM-NEXT: SymbolType: XTY_SD (0x1)
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; SYM-NEXT: StorageMappingClass: XMC_TE (0x16)
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; SYM-NEXT: Auxiliary Type: AUX_CSECT (0xFB)
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; SYM-NEXT: }
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; SYM: Index: 25
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; SYM-NEXT: Name: IThreadLocalVarUninit2
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; SYM-NEXT: Value (RelocatableAddress): 0xC0
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; SYM-NEXT: Section: .data
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; SYM-NEXT: Type: 0x0
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; SYM-NEXT: StorageClass: C_HIDEXT (0x6B)
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; SYM-NEXT: NumberOfAuxEntries: 1
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; SYM-NEXT: CSECT Auxiliary Entry {
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; SYM-NEXT: Index: 26
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; SYM-NEXT: SectionLen: 8
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; SYM-NEXT: ParameterHashIndex: 0x0
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; SYM-NEXT: TypeChkSectNum: 0x0
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; SYM-NEXT: SymbolAlignmentLog2: 3
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; SYM-NEXT: SymbolType: XTY_SD (0x1)
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; SYM-NEXT: StorageMappingClass: XMC_TE (0x16)
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; SYM-NEXT: Auxiliary Type: AUX_CSECT (0xFB)
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; SYM-NEXT: }
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; SYM-NEXT: }
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; SYM: Index: 27
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; SYM-NEXT: Name: ThreadLocalVarInit
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; SYM-NEXT: Value (RelocatableAddress): 0x0
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; SYM-NEXT: Section: .tdata
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; SYM-NEXT: Type: 0x0
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; SYM-NEXT: StorageClass: C_EXT (0x2)
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; SYM-NEXT: NumberOfAuxEntries: 1
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; SYM-NEXT: CSECT Auxiliary Entry {
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; SYM-NEXT: Index: 28
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; SYM-NEXT: SectionLen: 8
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; SYM-NEXT: ParameterHashIndex: 0x0
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; SYM-NEXT: TypeChkSectNum: 0x0
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; SYM-NEXT: SymbolAlignmentLog2: 3
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; SYM-NEXT: SymbolType: XTY_SD (0x1)
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; SYM-NEXT: StorageMappingClass: XMC_TL (0x14)
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; SYM-NEXT: Auxiliary Type: AUX_CSECT (0xFB)
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; SYM-NEXT: }
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; SYM-NEXT: }
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; SYM: Index: 29
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; SYM-NEXT: Name: IThreadLocalVarUninit
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; SYM-NEXT: Value (RelocatableAddress): 0x8
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; SYM-NEXT: Section: .tbss
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; SYM-NEXT: Type: 0x0
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; SYM-NEXT: StorageClass: C_HIDEXT (0x6B)
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; SYM-NEXT: NumberOfAuxEntries: 1
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; SYM-NEXT: CSECT Auxiliary Entry {
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; SYM-NEXT: Index: 30
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; SYM-NEXT: SectionLen: 8
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; SYM-NEXT: ParameterHashIndex: 0x0
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; SYM-NEXT: TypeChkSectNum: 0x0
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; SYM-NEXT: SymbolAlignmentLog2: 3
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; SYM-NEXT: SymbolType: XTY_CM (0x3)
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; SYM-NEXT: StorageMappingClass: XMC_UL (0x15)
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; SYM-NEXT: Auxiliary Type: AUX_CSECT (0xFB)
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; SYM-NEXT: }
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; SYM-NEXT: }
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; SYM: Index: 31
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; SYM-NEXT: Name: IThreadLocalVarUninit2
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; SYM-NEXT: Value (RelocatableAddress): 0x10
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; SYM-NEXT: Section: .tbss
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; SYM-NEXT: Type: 0x0
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; SYM-NEXT: StorageClass: C_HIDEXT (0x6B)
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; SYM-NEXT: NumberOfAuxEntries: 1
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; SYM-NEXT: CSECT Auxiliary Entry {
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; SYM-NEXT: Index: 32
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; SYM-NEXT: SectionLen: 8
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; SYM-NEXT: ParameterHashIndex: 0x0
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; SYM-NEXT: TypeChkSectNum: 0x0
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; SYM-NEXT: SymbolAlignmentLog2: 3
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; SYM-NEXT: SymbolType: XTY_CM (0x3)
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; SYM-NEXT: StorageMappingClass: XMC_UL (0x15)
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; SYM-NEXT: Auxiliary Type: AUX_CSECT (0xFB)
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; SYM-NEXT: }
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; SYM-NEXT: }
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; DIS: {{.*}}aix-tls-le-xcoff-reloc-large.ll.tmp.o: file format aix5coff64-rs6000
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; DIS: Disassembly of section .text:
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; DIS: 0000000000000000 (idx: 3) .storeITLUninit:
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; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} addis 4, 2, 0
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; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: 19) IThreadLocalVarUninit[TE]
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; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} ld 4, 0(4)
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; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: 19) IThreadLocalVarUninit[TE]
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; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} stdx 3, 13, 4
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; DIS-NEXT: blr
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; DIS: 0000000000000010 (idx: 5) .loadTLInit:
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; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} addis 3, 2, 0
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; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: 21) ThreadLocalVarInit[TE]
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; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} addis 4, 2, 0
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; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: 23) VarInit[TE]
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; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} ld 3, 8(3)
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; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: 21) ThreadLocalVarInit[TE]
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; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} ld 4, 16(4)
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; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: 23) VarInit[TE]
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; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} ldx 3, 13, 3
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; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} ld 4, 0(4)
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; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} add 3, 4, 3
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; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} blr
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; DIS: 0000000000000030 (idx: 7) .loadTLUninit:
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; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} addis 3, 2, 0
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; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: 19) IThreadLocalVarUninit[TE]
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; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} li 4, 1
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; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} ld 3, 0(3)
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; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: 19) IThreadLocalVarUninit[TE]
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; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} stdx 4, 13, 3
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; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} addis 3, 2, 0
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; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: 25) IThreadLocalVarUninit2[TE]
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; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} ld 3, 24(3)
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; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: 25) IThreadLocalVarUninit2[TE]
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; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} ldx 3, 13, 3
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; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} addi 3, 3, 1
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; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} blr
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; DIS: Disassembly of section .data:
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; DIS: 0000000000000058 (idx: 9) VarInit[RW]:
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; DIS-NEXT: 58: 00 00 00 00
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; DIS-NEXT: 5c: 00 00 00 57
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; DIS: 0000000000000060 (idx: 11) storeITLUninit[DS]:
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; DIS-NEXT: 60: 00 00 00 00
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; DIS-NEXT: 0000000000000060: R_POS (idx: 3) .storeITLUninit
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; DIS-NEXT: 64: 00 00 00 00
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; DIS-NEXT: 68: 00 00 00 00
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; DIS-NEXT: 0000000000000068: R_POS (idx: 17) TOC[TC0]
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; DIS-NEXT: 6c: 00 00 00 a8
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; DIS: 0000000000000078 (idx: 13) loadTLInit[DS]:
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; DIS-NEXT: 78: 00 00 00 00
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; DIS-NEXT: 0000000000000078: R_POS (idx: 5) .loadTLInit
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; DIS-NEXT: 7c: 00 00 00 10
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; DIS-NEXT: 80: 00 00 00 00
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; DIS-NEXT: 0000000000000080: R_POS (idx: 17) TOC[TC0]
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; DIS-NEXT: 84: 00 00 00 a8
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; DIS: 0000000000000090 (idx: 15) loadTLUninit[DS]:
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; DIS-NEXT: 90: 00 00 00 00
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; DIS-NEXT: 0000000000000090: R_POS (idx: 7) .loadTLUninit
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; DIS-NEXT: 94: 00 00 00 30
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; DIS-NEXT: 98: 00 00 00 00
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; DIS-NEXT: 0000000000000098: R_POS (idx: 17) TOC[TC0]
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; DIS-NEXT: 9c: 00 00 00 a8
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; DIS: 00000000000000a8 (idx: 19) IThreadLocalVarUninit[TE]:
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; DIS-NEXT: a8: 00 00 00 00
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; DIS-NEXT: 00000000000000a8: R_TLS_LE (idx: 29) IThreadLocalVarUninit[UL]
|
||
|
|
; DIS-NEXT: ac: 00 00 00 08
|
||
|
|
; DIS: 00000000000000b0 (idx: 21) ThreadLocalVarInit[TE]:
|
||
|
|
; DIS-NEXT: b0: 00 00 00 00
|
||
|
|
; DIS-NEXT: 00000000000000b0: R_TLS_LE (idx: 27) ThreadLocalVarInit[TL]
|
||
|
|
; DIS-NEXT: b4: 00 00 00 00
|
||
|
|
; DIS: 00000000000000b8 (idx: 23) VarInit[TE]:
|
||
|
|
; DIS-NEXT: b8: 00 00 00 00
|
||
|
|
; DIS-NEXT: 00000000000000b8: R_POS (idx: 9) VarInit[RW]
|
||
|
|
; DIS-NEXT: bc: 00 00 00 58
|
||
|
|
; DIS: 00000000000000c0 (idx: 25) IThreadLocalVarUninit2[TE]:
|
||
|
|
; DIS-NEXT: c0: 00 00 00 00
|
||
|
|
; DIS-NEXT: 00000000000000c0: R_TLS_LE (idx: 31) IThreadLocalVarUninit2[UL]
|
||
|
|
; DIS-NEXT: c4: 00 00 00 10
|
||
|
|
|
||
|
|
; DIS: Disassembly of section .tdata:
|
||
|
|
; DIS: 0000000000000000 (idx: 27) ThreadLocalVarInit[TL]:
|
||
|
|
; DIS-NEXT: 0: 00 00 00 00
|
||
|
|
; DIS-NEXT: 4: 00 00 00 01
|
||
|
|
|
||
|
|
; DIS: Disassembly of section .tbss:
|
||
|
|
; DIS: 0000000000000008 (idx: 29) IThreadLocalVarUninit[UL]:
|
||
|
|
; DIS-NEXT: ...
|
||
|
|
; DIS: 0000000000000010 (idx: 31) IThreadLocalVarUninit2[UL]:
|
||
|
|
; DIS-NEXT: ...
|
||
|
|
|