139 lines
3.5 KiB
LLVM
139 lines
3.5 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names < %s | FileCheck %s
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; Check that the brh/brw/brd instructions are generated for the bswap
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; intrinsic for register operand on P10 and that the lhbrx/lwbrx/ldbrw
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; instructions are generated for memory operand.
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declare i16 @llvm.bswap.i16(i16)
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define zeroext i16 @test_nomem16(i16 zeroext %a) {
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; CHECK-LABEL: test_nomem16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: brh r3, r3
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; CHECK-NEXT: clrldi r3, r3, 48
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; CHECK-NEXT: blr
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entry:
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%0 = tail call i16 @llvm.bswap.i16(i16 %a)
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ret i16 %0
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}
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declare i32 @llvm.bswap.i32(i32)
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define zeroext i32 @test_nomem32(i32 zeroext %a) {
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; CHECK-LABEL: test_nomem32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: brw r3, r3
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; CHECK-NEXT: clrldi r3, r3, 32
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; CHECK-NEXT: blr
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entry:
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%0 = tail call i32 @llvm.bswap.i32(i32 %a)
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ret i32 %0
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}
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; Check that brh and clrldi are produced from a call to @llvm.bswap.i32
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; followed by a right shift of 16 (and a zero-extend at the end of the DAG).
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define zeroext i32 @test_bswap_shift16(i32 zeroext %a) {
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; CHECK-LABEL: test_bswap_shift16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: brh r3, r3
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; CHECK-NEXT: clrldi r3, r3, 48
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; CHECK-NEXT: blr
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entry:
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%0 = tail call i32 @llvm.bswap.i32(i32 %a)
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%shr = lshr i32 %0, 16
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ret i32 %shr
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}
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; Check that brh are produced from a call to @llvm.bswap.i32
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; followed by a right shift of 16.
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declare i64 @call_1()
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define void @test_bswap_shift16_2() {
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; CHECK-LABEL: test_bswap_shift16_2:
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; CHECK: # %bb.0: # %bb
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; CHECK-NEXT: mflr r0
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; CHECK-NEXT: std r0, 16(r1)
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; CHECK-NEXT: stdu r1, -32(r1)
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: .cfi_offset lr, 16
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; CHECK-NEXT: bl call_1@notoc
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; CHECK-NEXT: brh r3, r3
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; CHECK-NEXT: rldicl r3, r3, 0, 48
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; CHECK-NEXT: sth r3, 0(r3)
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bb:
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switch i32 undef, label %bb1 [
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i32 78, label %bb2
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]
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bb1:
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unreachable
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bb2:
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%i = call i64 @call_1()
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%i3 = trunc i64 %i to i32
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%i4 = call i32 @llvm.bswap.i32(i32 %i3)
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%i5 = lshr i32 %i4, 16
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%i6 = trunc i32 %i5 to i16
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store i16 %i6, ptr undef, align 2
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unreachable
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}
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define zeroext i32 @test_bswap_shift18(i32 zeroext %a) {
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; CHECK-LABEL: test_bswap_shift18:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: brw r3, r3
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; CHECK-NEXT: rlwinm r3, r3, 14, 18, 31
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; CHECK-NEXT: blr
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entry:
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%0 = tail call i32 @llvm.bswap.i32(i32 %a)
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%shr = lshr i32 %0, 18
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ret i32 %shr
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}
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declare i64 @llvm.bswap.i64(i64)
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define i64 @test_nomem64(i64 %a) {
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; CHECK-LABEL: test_nomem64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: brd r3, r3
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; CHECK-NEXT: blr
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entry:
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%0 = tail call i64 @llvm.bswap.i64(i64 %a)
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ret i64 %0
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}
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define i16 @test_mem16(ptr %a) {
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; CHECK-LABEL: test_mem16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lhbrx r3, 0, r3
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; CHECK-NEXT: blr
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entry:
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%0 = load i16, ptr %a, align 2
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%1 = tail call i16 @llvm.bswap.i16(i16 %0)
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ret i16 %1
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}
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define i32 @test_mem32(ptr %a) {
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; CHECK-LABEL: test_mem32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lwbrx r3, 0, r3
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; CHECK-NEXT: blr
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entry:
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%0 = load i32, ptr %a, align 4
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%1 = tail call i32 @llvm.bswap.i32(i32 %0)
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ret i32 %1
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}
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define i64 @test_mem64(ptr %a) {
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; CHECK-LABEL: test_mem64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: ldbrx r3, 0, r3
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; CHECK-NEXT: blr
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entry:
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%0 = load i64, ptr %a, align 8
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%1 = tail call i64 @llvm.bswap.i64(i64 %0)
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ret i64 %1
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}
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