85 lines
2.9 KiB
LLVM
85 lines
2.9 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs\
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; RUN: -mcpu=pwr9 --ppc-enable-pipeliner 2>&1 | FileCheck %s
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; Test that the pipeliner schedules the store instructions correctly. Since
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; there is a dependence between the store, they cannot be scheduled further than
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; MII cycles/instructions apart. That is, the first store cannot occur multiple
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; times before the second ctore in the schedule.
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define dso_local void @comp_method(ptr noalias nocapture noundef readonly %0, ptr nocapture noundef writeonly %1, ptr nocapture noundef writeonly %2, i32 noundef %3, i32 noundef %4, i32 noundef %5, i32 noundef %6, i64 %v1) local_unnamed_addr {
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; CHECK-LABEL: comp_method:
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; CHECK: # %bb.0:
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; CHECK-NEXT: extsw 7, 8
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; CHECK-NEXT: extsw 8, 9
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; CHECK-NEXT: clrldi 9, 6, 32
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; CHECK-NEXT: addi 6, 3, -1
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; CHECK-NEXT: mtctr 9
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; CHECK-NEXT: li 11, 0
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; CHECK-NEXT: sradi 12, 11, 2
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; CHECK-NEXT: add 5, 5, 8
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; CHECK-NEXT: li 8, 2
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; CHECK-NEXT: li 3, 8
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; CHECK-NEXT: addi 11, 7, 0
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; CHECK-NEXT: std 30, -16(1) # 8-byte Folded Spill
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; CHECK-NEXT: lbzu 9, 1(6)
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; CHECK-NEXT: add 12, 12, 10
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; CHECK-NEXT: extsb 9, 9
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; CHECK-NEXT: stbx 8, 4, 9
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; CHECK-NEXT: add 9, 9, 12
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; CHECK-NEXT: bdz .LBB0_2
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; CHECK-NEXT: .p2align 4
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; CHECK-NEXT: .LBB0_1:
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; CHECK-NEXT: lbzu 0, 1(6)
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; CHECK-NEXT: sradi 12, 11, 2
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; CHECK-NEXT: add 11, 11, 7
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; CHECK-NEXT: add 12, 12, 10
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; CHECK-NEXT: sldi 30, 9, 2
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; CHECK-NEXT: add 9, 9, 30
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; CHECK-NEXT: extsb 0, 0
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; CHECK-NEXT: stbx 3, 5, 9
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; CHECK-NEXT: add 9, 0, 12
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; CHECK-NEXT: stbx 8, 4, 0
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; CHECK-NEXT: bdnz .LBB0_1
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; CHECK-NEXT: .LBB0_2:
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; CHECK-NEXT: sldi 4, 9, 2
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; CHECK-NEXT: ld 30, -16(1) # 8-byte Folded Reload
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; CHECK-NEXT: add 4, 9, 4
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; CHECK-NEXT: stbx 3, 5, 4
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; CHECK-NEXT: blr
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%8 = icmp sgt i32 %3, 64
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tail call void @llvm.assume(i1 %8)
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%9 = and i32 %3, 1
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%10 = icmp eq i32 %9, 0
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tail call void @llvm.assume(i1 %10)
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%11 = sext i32 %5 to i64
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%12 = sext i32 %6 to i64
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%13 = zext nneg i32 %3 to i64
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%14 = getelementptr i8, ptr %2, i64 %12
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br label %16
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15:
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ret void
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16:
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%17 = phi i64 [ 0, %7 ], [ %24, %16 ]
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%18 = getelementptr inbounds i8, ptr %0, i64 %17
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%19 = load i8, ptr %18, align 1
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%20 = sext i8 %19 to i64
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%21 = getelementptr inbounds i8, ptr %1, i64 %20
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store i8 2, ptr %21, align 1
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%22 = mul nsw i64 %17, %11
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%a1 = ashr i64 %22, 2
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%a2 = add i64 %a1, %v1
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%a3 = add i64 %20, %a2
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%a4 = mul nsw i64 %a3, 5
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%23 = getelementptr i8, ptr %14, i64 %a4
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store i8 8, ptr %23, align 1
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%24 = add nuw nsw i64 %17, 1
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%25 = icmp eq i64 %24, %13
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br i1 %25, label %15, label %16
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}
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declare void @llvm.assume(i1 noundef) #1
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attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) }
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