182 lines
6.3 KiB
Text
182 lines
6.3 KiB
Text
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=regbankselect \
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# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
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# RUN: -o - | FileCheck -check-prefix=RV32I %s
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---
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name: fp_select_s32
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $x10, $f10_f, $f11_f
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; RV32I-LABEL: name: fp_select_s32
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; RV32I: liveins: $x10, $f10_f, $f11_f
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; RV32I-NEXT: {{ $}}
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; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
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; RV32I-NEXT: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f10_f
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; RV32I-NEXT: [[COPY2:%[0-9]+]]:fprb(s32) = COPY $f11_f
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; RV32I-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
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; RV32I-NEXT: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY]], [[C]]
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; RV32I-NEXT: [[SELECT:%[0-9]+]]:fprb(s32) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]]
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; RV32I-NEXT: $f10_f = COPY [[SELECT]](s32)
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; RV32I-NEXT: PseudoRET implicit $f10_f
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%3:_(s32) = COPY $x10
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%4:_(s32) = COPY $f10_f
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%5:_(s32) = COPY $f11_f
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%12:_(s32) = G_CONSTANT i32 1
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%11:_(s32) = G_AND %3, %12
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%10:_(s32) = G_SELECT %11(s32), %4, %5
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$f10_f = COPY %10(s32)
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PseudoRET implicit $f10_f
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...
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---
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name: fp_select_s64
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $x10, $f10_d, $f11_d
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; RV32I-LABEL: name: fp_select_s64
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; RV32I: liveins: $x10, $f10_d, $f11_d
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; RV32I-NEXT: {{ $}}
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; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
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; RV32I-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f10_d
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; RV32I-NEXT: [[COPY2:%[0-9]+]]:fprb(s64) = COPY $f11_d
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; RV32I-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
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; RV32I-NEXT: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY]], [[C]]
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; RV32I-NEXT: [[SELECT:%[0-9]+]]:fprb(s64) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]]
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; RV32I-NEXT: $f10_d = COPY [[SELECT]](s64)
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; RV32I-NEXT: PseudoRET implicit $f10_d
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%3:_(s32) = COPY $x10
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%4:_(s64) = COPY $f10_d
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%5:_(s64) = COPY $f11_d
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%12:_(s32) = G_CONSTANT i32 1
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%11:_(s32) = G_AND %3, %12
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%10:_(s64) = G_SELECT %11(s32), %4, %5
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$f10_d = COPY %10(s64)
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PseudoRET implicit $f10_d
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...
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---
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name: fp_select_gpr_use_s32
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $x10, $f10_f, $f11_f
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; RV32I-LABEL: name: fp_select_gpr_use_s32
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; RV32I: liveins: $x10, $f10_f, $f11_f
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; RV32I-NEXT: {{ $}}
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; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
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; RV32I-NEXT: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f10_f
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; RV32I-NEXT: [[COPY2:%[0-9]+]]:fprb(s32) = COPY $f11_f
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; RV32I-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
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; RV32I-NEXT: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY]], [[C]]
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; RV32I-NEXT: [[SELECT:%[0-9]+]]:fprb(s32) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]]
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; RV32I-NEXT: $x10 = COPY [[SELECT]](s32)
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; RV32I-NEXT: PseudoRET implicit $x10
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%3:_(s32) = COPY $x10
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%4:_(s32) = COPY $f10_f
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%5:_(s32) = COPY $f11_f
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%12:_(s32) = G_CONSTANT i32 1
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%11:_(s32) = G_AND %3, %12
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%10:_(s32) = G_SELECT %11(s32), %4, %5
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$x10 = COPY %10(s32)
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PseudoRET implicit $x10
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...
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---
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name: fp_select_gpr_def_s32
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $x10, $x11, $f10_f
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; RV32I-LABEL: name: fp_select_gpr_def_s32
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; RV32I: liveins: $x10, $x11, $f10_f
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; RV32I-NEXT: {{ $}}
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; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
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; RV32I-NEXT: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f10_f
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; RV32I-NEXT: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $x11
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; RV32I-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
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; RV32I-NEXT: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY]], [[C]]
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; RV32I-NEXT: [[COPY3:%[0-9]+]]:fprb(s32) = COPY [[COPY2]](s32)
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; RV32I-NEXT: [[SELECT:%[0-9]+]]:fprb(s32) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY3]]
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; RV32I-NEXT: $f10_f = COPY [[SELECT]](s32)
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; RV32I-NEXT: PseudoRET implicit $f10_f
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%3:_(s32) = COPY $x10
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%4:_(s32) = COPY $f10_f
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%5:_(s32) = COPY $x11
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%12:_(s32) = G_CONSTANT i32 1
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%11:_(s32) = G_AND %3, %12
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%10:_(s32) = G_SELECT %11(s32), %4, %5
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$f10_f = COPY %10(s32)
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PseudoRET implicit $f10_f
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...
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---
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name: fp_select_only_fpr_use_s32
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $x10, $x11, $x12
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; RV32I-LABEL: name: fp_select_only_fpr_use_s32
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; RV32I: liveins: $x10, $x11, $x12
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; RV32I-NEXT: {{ $}}
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; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
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; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
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; RV32I-NEXT: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $x12
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; RV32I-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
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; RV32I-NEXT: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY]], [[C]]
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; RV32I-NEXT: [[SELECT:%[0-9]+]]:gprb(s32) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]]
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; RV32I-NEXT: $f10_f = COPY [[SELECT]](s32)
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; RV32I-NEXT: PseudoRET implicit $f10_f
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%3:_(s32) = COPY $x10
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%4:_(s32) = COPY $x11
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%5:_(s32) = COPY $x12
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%12:_(s32) = G_CONSTANT i32 1
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%11:_(s32) = G_AND %3, %12
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%10:_(s32) = G_SELECT %11(s32), %4, %5
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$f10_f = COPY %10(s32)
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PseudoRET implicit $f10_f
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...
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---
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name: fp_select_only_one_fpr_def_s32
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $x10, $x11, $f10_f
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; RV32I-LABEL: name: fp_select_only_one_fpr_def_s32
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; RV32I: liveins: $x10, $x11, $f10_f
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; RV32I-NEXT: {{ $}}
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; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
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; RV32I-NEXT: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f10_f
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; RV32I-NEXT: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $x11
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; RV32I-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
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; RV32I-NEXT: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY]], [[C]]
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; RV32I-NEXT: [[COPY3:%[0-9]+]]:gprb(s32) = COPY [[COPY1]](s32)
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; RV32I-NEXT: [[SELECT:%[0-9]+]]:gprb(s32) = G_SELECT [[AND]](s32), [[COPY3]], [[COPY2]]
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; RV32I-NEXT: $x10 = COPY [[SELECT]](s32)
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; RV32I-NEXT: PseudoRET implicit $x10
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%3:_(s32) = COPY $x10
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%4:_(s32) = COPY $f10_f
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%5:_(s32) = COPY $x11
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%12:_(s32) = G_CONSTANT i32 1
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%11:_(s32) = G_AND %3, %12
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%10:_(s32) = G_SELECT %11(s32), %4, %5
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$x10 = COPY %10(s32)
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PseudoRET implicit $x10
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...
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