188 lines
5.6 KiB
LLVM
188 lines
5.6 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefixes=RV32
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefixes=RV64
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define i32 @optbranch_32(i32 %Arg) {
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; RV32-LABEL: optbranch_32:
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; RV32: # %bb.0: # %bb
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; RV32-NEXT: addi a0, a0, 1
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; RV32-NEXT: bnez a0, .LBB0_2
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; RV32-NEXT: # %bb.1: # %bb2
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; RV32-NEXT: li a0, -1
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; RV32-NEXT: .LBB0_2: # %bb3
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; RV32-NEXT: ret
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;
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; RV64-LABEL: optbranch_32:
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; RV64: # %bb.0: # %bb
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; RV64-NEXT: addiw a0, a0, 1
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; RV64-NEXT: bnez a0, .LBB0_2
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; RV64-NEXT: # %bb.1: # %bb2
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; RV64-NEXT: li a0, -1
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; RV64-NEXT: .LBB0_2: # %bb3
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; RV64-NEXT: ret
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bb:
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%i1 = icmp eq i32 %Arg, -1
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br i1 %i1, label %bb2, label %bb3
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bb2:
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ret i32 -1
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bb3:
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%i4 = add nuw i32 %Arg, 1
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ret i32 %i4
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}
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define i64 @optbranch_64(i64 %Arg) {
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; RV32-LABEL: optbranch_64:
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; RV32: # %bb.0: # %bb
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; RV32-NEXT: addi a0, a0, 1
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; RV32-NEXT: seqz a2, a0
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; RV32-NEXT: add a1, a1, a2
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; RV32-NEXT: or a2, a0, a1
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; RV32-NEXT: bnez a2, .LBB1_2
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; RV32-NEXT: # %bb.1: # %bb2
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; RV32-NEXT: li a0, -1
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; RV32-NEXT: li a1, -1
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; RV32-NEXT: .LBB1_2: # %bb3
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; RV32-NEXT: ret
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;
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; RV64-LABEL: optbranch_64:
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; RV64: # %bb.0: # %bb
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; RV64-NEXT: addi a0, a0, 1
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; RV64-NEXT: bnez a0, .LBB1_2
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; RV64-NEXT: # %bb.1: # %bb2
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; RV64-NEXT: li a0, -1
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; RV64-NEXT: .LBB1_2: # %bb3
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; RV64-NEXT: ret
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bb:
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%i1 = icmp eq i64 %Arg, -1
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br i1 %i1, label %bb2, label %bb3
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bb2:
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ret i64 -1
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bb3:
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%i4 = add nuw i64 %Arg, 1
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ret i64 %i4
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}
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define i32 @test_lshr(i32 %v) {
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; RV32-LABEL: test_lshr:
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; RV32: # %bb.0: # %entry
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; RV32-NEXT: li a1, 0
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; RV32-NEXT: beqz a0, .LBB2_2
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; RV32-NEXT: .LBB2_1: # %for.body
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; RV32-NEXT: # =>This Inner Loop Header: Depth=1
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; RV32-NEXT: andi a2, a0, 1
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; RV32-NEXT: srli a0, a0, 1
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; RV32-NEXT: add a1, a1, a2
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; RV32-NEXT: bnez a0, .LBB2_1
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; RV32-NEXT: .LBB2_2: # %for.end
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; RV32-NEXT: mv a0, a1
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test_lshr:
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; RV64: # %bb.0: # %entry
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; RV64-NEXT: sext.w a1, a0
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; RV64-NEXT: beqz a1, .LBB2_3
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; RV64-NEXT: # %bb.1: # %for.body.preheader
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; RV64-NEXT: li a1, 0
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; RV64-NEXT: .LBB2_2: # %for.body
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; RV64-NEXT: # =>This Inner Loop Header: Depth=1
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; RV64-NEXT: andi a2, a0, 1
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; RV64-NEXT: srliw a0, a0, 1
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; RV64-NEXT: addw a1, a1, a2
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; RV64-NEXT: bnez a0, .LBB2_2
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; RV64-NEXT: .LBB2_3: # %for.end
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; RV64-NEXT: mv a0, a1
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; RV64-NEXT: ret
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entry:
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%tobool.not4 = icmp eq i32 %v, 0
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br i1 %tobool.not4, label %for.end, label %for.body
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for.body: ; preds = %entry, %for.body
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%c.06 = phi i32 [ %add, %for.body ], [ 0, %entry ]
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%v.addr.05 = phi i32 [ %shr, %for.body ], [ %v, %entry ]
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%and = and i32 %v.addr.05, 1
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%add = add i32 %c.06, %and
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%shr = lshr i32 %v.addr.05, 1
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%tobool.not = icmp ult i32 %v.addr.05, 2
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br i1 %tobool.not, label %for.end, label %for.body
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for.end: ; preds = %for.body, %entry
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%c.0.lcssa = phi i32 [ 0, %entry ], [ %add, %for.body ]
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ret i32 %c.0.lcssa
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}
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define i32 @test_lshr2(ptr nocapture %x, ptr nocapture readonly %y, i32 %n) {
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; RV32-LABEL: test_lshr2:
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; RV32: # %bb.0: # %entry
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; RV32-NEXT: srli a2, a2, 2
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; RV32-NEXT: beqz a2, .LBB3_3
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; RV32-NEXT: # %bb.1: # %while.body.preheader
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; RV32-NEXT: slli a2, a2, 2
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; RV32-NEXT: add a2, a1, a2
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; RV32-NEXT: .LBB3_2: # %while.body
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; RV32-NEXT: # =>This Inner Loop Header: Depth=1
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; RV32-NEXT: lw a3, 0(a1)
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; RV32-NEXT: addi a4, a1, 4
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; RV32-NEXT: slli a3, a3, 1
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; RV32-NEXT: addi a1, a0, 4
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; RV32-NEXT: sw a3, 0(a0)
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; RV32-NEXT: mv a0, a1
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; RV32-NEXT: mv a1, a4
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; RV32-NEXT: bne a4, a2, .LBB3_2
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; RV32-NEXT: .LBB3_3: # %while.end
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; RV32-NEXT: li a0, 0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test_lshr2:
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; RV64: # %bb.0: # %entry
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; RV64-NEXT: srliw a2, a2, 2
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; RV64-NEXT: beqz a2, .LBB3_3
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; RV64-NEXT: # %bb.1: # %while.body.preheader
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; RV64-NEXT: addi a2, a2, -1
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; RV64-NEXT: slli a2, a2, 32
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; RV64-NEXT: srli a2, a2, 30
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; RV64-NEXT: add a2, a2, a1
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; RV64-NEXT: addi a2, a2, 4
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; RV64-NEXT: .LBB3_2: # %while.body
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; RV64-NEXT: # =>This Inner Loop Header: Depth=1
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; RV64-NEXT: lw a3, 0(a1)
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; RV64-NEXT: addi a4, a1, 4
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; RV64-NEXT: slli a3, a3, 1
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; RV64-NEXT: addi a1, a0, 4
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; RV64-NEXT: sw a3, 0(a0)
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; RV64-NEXT: mv a0, a1
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; RV64-NEXT: mv a1, a4
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; RV64-NEXT: bne a4, a2, .LBB3_2
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; RV64-NEXT: .LBB3_3: # %while.end
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; RV64-NEXT: li a0, 0
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; RV64-NEXT: ret
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entry:
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%tobool.not4 = icmp ult i32 %n, 4
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br i1 %tobool.not4, label %while.end, label %while.body.preheader
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while.body.preheader: ; preds = %entry
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%shr = lshr i32 %n, 2
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br label %while.body
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while.body: ; preds = %while.body.preheader, %while.body
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%c.07 = phi i32 [ %dec, %while.body ], [ %shr, %while.body.preheader ]
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%x.addr.06 = phi ptr [ %incdec.ptr1, %while.body ], [ %x, %while.body.preheader ]
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%y.addr.05 = phi ptr [ %incdec.ptr, %while.body ], [ %y, %while.body.preheader ]
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%incdec.ptr = getelementptr inbounds i32, ptr %y.addr.05, i32 1
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%0 = load i32, ptr %y.addr.05, align 4
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%mul = shl nsw i32 %0, 1
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%incdec.ptr1 = getelementptr inbounds i32, ptr %x.addr.06, i32 1
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store i32 %mul, ptr %x.addr.06, align 4
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%dec = add nsw i32 %c.07, -1
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%tobool.not = icmp eq i32 %dec, 0
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br i1 %tobool.not, label %while.end, label %while.body
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while.end: ; preds = %while.body, %entry
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ret i32 0
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}
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