378 lines
14 KiB
LLVM
378 lines
14 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d \
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; RUN: -verify-machineinstrs -target-abi=ilp32d \
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; RUN: | FileCheck -check-prefixes=CHECKIFD,RV32IFD %s
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; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d \
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; RUN: -verify-machineinstrs -target-abi=lp64d \
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; RUN: | FileCheck -check-prefixes=CHECKIFD,RV64IFD %s
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; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zdinx \
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; RUN: -verify-machineinstrs -target-abi=ilp32 \
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; RUN: | FileCheck -check-prefix=RV32IZFINXZDINX %s
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; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zdinx \
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; RUN: -verify-machineinstrs -target-abi=lp64 \
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; RUN: | FileCheck -check-prefix=RV64IZFINXZDINX %s
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declare double @llvm.minimum.f64(double, double)
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define double @fminimum_f64(double %a, double %b) nounwind {
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; CHECKIFD-LABEL: fminimum_f64:
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; CHECKIFD: # %bb.0:
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; CHECKIFD-NEXT: feq.d a0, fa0, fa0
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; CHECKIFD-NEXT: fmv.d fa5, fa1
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; CHECKIFD-NEXT: beqz a0, .LBB0_3
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; CHECKIFD-NEXT: # %bb.1:
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; CHECKIFD-NEXT: feq.d a0, fa1, fa1
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; CHECKIFD-NEXT: beqz a0, .LBB0_4
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; CHECKIFD-NEXT: .LBB0_2:
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; CHECKIFD-NEXT: fmin.d fa0, fa0, fa5
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; CHECKIFD-NEXT: ret
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; CHECKIFD-NEXT: .LBB0_3:
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; CHECKIFD-NEXT: fmv.d fa5, fa0
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; CHECKIFD-NEXT: feq.d a0, fa1, fa1
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; CHECKIFD-NEXT: bnez a0, .LBB0_2
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; CHECKIFD-NEXT: .LBB0_4:
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; CHECKIFD-NEXT: fmin.d fa0, fa1, fa5
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; CHECKIFD-NEXT: ret
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;
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; RV32IZFINXZDINX-LABEL: fminimum_f64:
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; RV32IZFINXZDINX: # %bb.0:
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; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
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; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
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; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
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; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
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; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
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; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
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; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
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; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
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; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
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; RV32IZFINXZDINX-NEXT: feq.d a6, a0, a0
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; RV32IZFINXZDINX-NEXT: mv a4, a2
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; RV32IZFINXZDINX-NEXT: mv a5, a3
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; RV32IZFINXZDINX-NEXT: bnez a6, .LBB0_2
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; RV32IZFINXZDINX-NEXT: # %bb.1:
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; RV32IZFINXZDINX-NEXT: mv a4, a0
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; RV32IZFINXZDINX-NEXT: mv a5, a1
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; RV32IZFINXZDINX-NEXT: .LBB0_2:
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; RV32IZFINXZDINX-NEXT: feq.d a6, a2, a2
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; RV32IZFINXZDINX-NEXT: bnez a6, .LBB0_4
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; RV32IZFINXZDINX-NEXT: # %bb.3:
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; RV32IZFINXZDINX-NEXT: mv a0, a2
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; RV32IZFINXZDINX-NEXT: mv a1, a3
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; RV32IZFINXZDINX-NEXT: .LBB0_4:
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; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a4
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; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
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; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
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; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
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; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
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; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
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; RV32IZFINXZDINX-NEXT: ret
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;
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; RV64IZFINXZDINX-LABEL: fminimum_f64:
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; RV64IZFINXZDINX: # %bb.0:
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; RV64IZFINXZDINX-NEXT: feq.d a3, a0, a0
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; RV64IZFINXZDINX-NEXT: mv a2, a1
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; RV64IZFINXZDINX-NEXT: beqz a3, .LBB0_3
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; RV64IZFINXZDINX-NEXT: # %bb.1:
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; RV64IZFINXZDINX-NEXT: feq.d a3, a1, a1
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; RV64IZFINXZDINX-NEXT: beqz a3, .LBB0_4
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; RV64IZFINXZDINX-NEXT: .LBB0_2:
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; RV64IZFINXZDINX-NEXT: fmin.d a0, a0, a2
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; RV64IZFINXZDINX-NEXT: ret
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; RV64IZFINXZDINX-NEXT: .LBB0_3:
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; RV64IZFINXZDINX-NEXT: mv a2, a0
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; RV64IZFINXZDINX-NEXT: feq.d a3, a1, a1
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; RV64IZFINXZDINX-NEXT: bnez a3, .LBB0_2
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; RV64IZFINXZDINX-NEXT: .LBB0_4:
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; RV64IZFINXZDINX-NEXT: fmin.d a0, a1, a2
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; RV64IZFINXZDINX-NEXT: ret
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%1 = call double @llvm.minimum.f64(double %a, double %b)
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ret double %1
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}
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declare double @llvm.maximum.f64(double, double)
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define double @fmaximum_f64(double %a, double %b) nounwind {
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; CHECKIFD-LABEL: fmaximum_f64:
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; CHECKIFD: # %bb.0:
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; CHECKIFD-NEXT: feq.d a0, fa0, fa0
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; CHECKIFD-NEXT: fmv.d fa5, fa1
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; CHECKIFD-NEXT: beqz a0, .LBB1_3
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; CHECKIFD-NEXT: # %bb.1:
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; CHECKIFD-NEXT: feq.d a0, fa1, fa1
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; CHECKIFD-NEXT: beqz a0, .LBB1_4
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; CHECKIFD-NEXT: .LBB1_2:
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; CHECKIFD-NEXT: fmax.d fa0, fa0, fa5
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; CHECKIFD-NEXT: ret
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; CHECKIFD-NEXT: .LBB1_3:
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; CHECKIFD-NEXT: fmv.d fa5, fa0
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; CHECKIFD-NEXT: feq.d a0, fa1, fa1
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; CHECKIFD-NEXT: bnez a0, .LBB1_2
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; CHECKIFD-NEXT: .LBB1_4:
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; CHECKIFD-NEXT: fmax.d fa0, fa1, fa5
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; CHECKIFD-NEXT: ret
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;
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; RV32IZFINXZDINX-LABEL: fmaximum_f64:
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; RV32IZFINXZDINX: # %bb.0:
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; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
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; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
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; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
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; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
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; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
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; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
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; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
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; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
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; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
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; RV32IZFINXZDINX-NEXT: feq.d a6, a0, a0
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; RV32IZFINXZDINX-NEXT: mv a4, a2
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; RV32IZFINXZDINX-NEXT: mv a5, a3
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; RV32IZFINXZDINX-NEXT: bnez a6, .LBB1_2
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; RV32IZFINXZDINX-NEXT: # %bb.1:
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; RV32IZFINXZDINX-NEXT: mv a4, a0
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; RV32IZFINXZDINX-NEXT: mv a5, a1
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; RV32IZFINXZDINX-NEXT: .LBB1_2:
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; RV32IZFINXZDINX-NEXT: feq.d a6, a2, a2
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; RV32IZFINXZDINX-NEXT: bnez a6, .LBB1_4
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; RV32IZFINXZDINX-NEXT: # %bb.3:
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; RV32IZFINXZDINX-NEXT: mv a0, a2
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; RV32IZFINXZDINX-NEXT: mv a1, a3
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; RV32IZFINXZDINX-NEXT: .LBB1_4:
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; RV32IZFINXZDINX-NEXT: fmax.d a0, a0, a4
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; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
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; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
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; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
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; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
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; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
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; RV32IZFINXZDINX-NEXT: ret
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;
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; RV64IZFINXZDINX-LABEL: fmaximum_f64:
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; RV64IZFINXZDINX: # %bb.0:
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; RV64IZFINXZDINX-NEXT: feq.d a3, a0, a0
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; RV64IZFINXZDINX-NEXT: mv a2, a1
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; RV64IZFINXZDINX-NEXT: beqz a3, .LBB1_3
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; RV64IZFINXZDINX-NEXT: # %bb.1:
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; RV64IZFINXZDINX-NEXT: feq.d a3, a1, a1
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; RV64IZFINXZDINX-NEXT: beqz a3, .LBB1_4
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; RV64IZFINXZDINX-NEXT: .LBB1_2:
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; RV64IZFINXZDINX-NEXT: fmax.d a0, a0, a2
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; RV64IZFINXZDINX-NEXT: ret
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; RV64IZFINXZDINX-NEXT: .LBB1_3:
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; RV64IZFINXZDINX-NEXT: mv a2, a0
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; RV64IZFINXZDINX-NEXT: feq.d a3, a1, a1
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; RV64IZFINXZDINX-NEXT: bnez a3, .LBB1_2
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; RV64IZFINXZDINX-NEXT: .LBB1_4:
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; RV64IZFINXZDINX-NEXT: fmax.d a0, a1, a2
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; RV64IZFINXZDINX-NEXT: ret
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%1 = call double @llvm.maximum.f64(double %a, double %b)
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ret double %1
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}
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define double @fminimum_nnan_f64(double %a, double %b) nounwind {
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; CHECKIFD-LABEL: fminimum_nnan_f64:
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; CHECKIFD: # %bb.0:
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; CHECKIFD-NEXT: fmin.d fa0, fa0, fa1
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; CHECKIFD-NEXT: ret
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;
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; RV32IZFINXZDINX-LABEL: fminimum_nnan_f64:
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; RV32IZFINXZDINX: # %bb.0:
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; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
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; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
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; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
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; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
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; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
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; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
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; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
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; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
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; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
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; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a2
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; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
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; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
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; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
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; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
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; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
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; RV32IZFINXZDINX-NEXT: ret
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;
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; RV64IZFINXZDINX-LABEL: fminimum_nnan_f64:
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; RV64IZFINXZDINX: # %bb.0:
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; RV64IZFINXZDINX-NEXT: fmin.d a0, a0, a1
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; RV64IZFINXZDINX-NEXT: ret
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%1 = call nnan double @llvm.minimum.f64(double %a, double %b)
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ret double %1
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}
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define double @fmaximum_nnan_f64(double %a, double %b) nounwind {
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; CHECKIFD-LABEL: fmaximum_nnan_f64:
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; CHECKIFD: # %bb.0:
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; CHECKIFD-NEXT: feq.d a0, fa0, fa0
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; CHECKIFD-NEXT: fmv.d fa5, fa1
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; CHECKIFD-NEXT: beqz a0, .LBB3_3
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; CHECKIFD-NEXT: # %bb.1:
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; CHECKIFD-NEXT: feq.d a0, fa1, fa1
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; CHECKIFD-NEXT: beqz a0, .LBB3_4
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; CHECKIFD-NEXT: .LBB3_2:
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; CHECKIFD-NEXT: fmin.d fa0, fa0, fa5
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; CHECKIFD-NEXT: ret
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; CHECKIFD-NEXT: .LBB3_3:
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; CHECKIFD-NEXT: fmv.d fa5, fa0
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; CHECKIFD-NEXT: feq.d a0, fa1, fa1
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; CHECKIFD-NEXT: bnez a0, .LBB3_2
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; CHECKIFD-NEXT: .LBB3_4:
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; CHECKIFD-NEXT: fmin.d fa0, fa1, fa5
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; CHECKIFD-NEXT: ret
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;
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; RV32IZFINXZDINX-LABEL: fmaximum_nnan_f64:
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; RV32IZFINXZDINX: # %bb.0:
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; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
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; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
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; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
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; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
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; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
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; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
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; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
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; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
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; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
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; RV32IZFINXZDINX-NEXT: feq.d a6, a0, a0
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; RV32IZFINXZDINX-NEXT: mv a4, a2
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; RV32IZFINXZDINX-NEXT: mv a5, a3
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; RV32IZFINXZDINX-NEXT: bnez a6, .LBB3_2
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; RV32IZFINXZDINX-NEXT: # %bb.1:
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; RV32IZFINXZDINX-NEXT: mv a4, a0
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; RV32IZFINXZDINX-NEXT: mv a5, a1
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; RV32IZFINXZDINX-NEXT: .LBB3_2:
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; RV32IZFINXZDINX-NEXT: feq.d a6, a2, a2
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; RV32IZFINXZDINX-NEXT: bnez a6, .LBB3_4
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; RV32IZFINXZDINX-NEXT: # %bb.3:
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; RV32IZFINXZDINX-NEXT: mv a0, a2
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; RV32IZFINXZDINX-NEXT: mv a1, a3
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; RV32IZFINXZDINX-NEXT: .LBB3_4:
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; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a4
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; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
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; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
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; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
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; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
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; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
|
||
|
|
; RV32IZFINXZDINX-NEXT: ret
|
||
|
|
;
|
||
|
|
; RV64IZFINXZDINX-LABEL: fmaximum_nnan_f64:
|
||
|
|
; RV64IZFINXZDINX: # %bb.0:
|
||
|
|
; RV64IZFINXZDINX-NEXT: feq.d a3, a0, a0
|
||
|
|
; RV64IZFINXZDINX-NEXT: mv a2, a1
|
||
|
|
; RV64IZFINXZDINX-NEXT: beqz a3, .LBB3_3
|
||
|
|
; RV64IZFINXZDINX-NEXT: # %bb.1:
|
||
|
|
; RV64IZFINXZDINX-NEXT: feq.d a3, a1, a1
|
||
|
|
; RV64IZFINXZDINX-NEXT: beqz a3, .LBB3_4
|
||
|
|
; RV64IZFINXZDINX-NEXT: .LBB3_2:
|
||
|
|
; RV64IZFINXZDINX-NEXT: fmin.d a0, a0, a2
|
||
|
|
; RV64IZFINXZDINX-NEXT: ret
|
||
|
|
; RV64IZFINXZDINX-NEXT: .LBB3_3:
|
||
|
|
; RV64IZFINXZDINX-NEXT: mv a2, a0
|
||
|
|
; RV64IZFINXZDINX-NEXT: feq.d a3, a1, a1
|
||
|
|
; RV64IZFINXZDINX-NEXT: bnez a3, .LBB3_2
|
||
|
|
; RV64IZFINXZDINX-NEXT: .LBB3_4:
|
||
|
|
; RV64IZFINXZDINX-NEXT: fmin.d a0, a1, a2
|
||
|
|
; RV64IZFINXZDINX-NEXT: ret
|
||
|
|
%1 = call double @llvm.minimum.f64(double %a, double %b)
|
||
|
|
ret double %1
|
||
|
|
}
|
||
|
|
|
||
|
|
define double @fminimum_nnan_op_f64(double %a, double %b) nounwind {
|
||
|
|
; CHECKIFD-LABEL: fminimum_nnan_op_f64:
|
||
|
|
; CHECKIFD: # %bb.0:
|
||
|
|
; CHECKIFD-NEXT: feq.d a0, fa1, fa1
|
||
|
|
; CHECKIFD-NEXT: bnez a0, .LBB4_2
|
||
|
|
; CHECKIFD-NEXT: # %bb.1:
|
||
|
|
; CHECKIFD-NEXT: fmin.d fa0, fa1, fa1
|
||
|
|
; CHECKIFD-NEXT: ret
|
||
|
|
; CHECKIFD-NEXT: .LBB4_2:
|
||
|
|
; CHECKIFD-NEXT: fadd.d fa5, fa0, fa0
|
||
|
|
; CHECKIFD-NEXT: fmin.d fa0, fa5, fa1
|
||
|
|
; CHECKIFD-NEXT: ret
|
||
|
|
;
|
||
|
|
; RV32IZFINXZDINX-LABEL: fminimum_nnan_op_f64:
|
||
|
|
; RV32IZFINXZDINX: # %bb.0:
|
||
|
|
; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
|
||
|
|
; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
|
||
|
|
; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
|
||
|
|
; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
|
||
|
|
; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
|
||
|
|
; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
|
||
|
|
; RV32IZFINXZDINX-NEXT: feq.d a0, a2, a2
|
||
|
|
; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
|
||
|
|
; RV32IZFINXZDINX-NEXT: bnez a0, .LBB4_2
|
||
|
|
; RV32IZFINXZDINX-NEXT: # %bb.1:
|
||
|
|
; RV32IZFINXZDINX-NEXT: mv a0, a2
|
||
|
|
; RV32IZFINXZDINX-NEXT: mv a1, a3
|
||
|
|
; RV32IZFINXZDINX-NEXT: j .LBB4_3
|
||
|
|
; RV32IZFINXZDINX-NEXT: .LBB4_2:
|
||
|
|
; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
|
||
|
|
; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
|
||
|
|
; RV32IZFINXZDINX-NEXT: fadd.d a0, a0, a0
|
||
|
|
; RV32IZFINXZDINX-NEXT: .LBB4_3:
|
||
|
|
; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a2
|
||
|
|
; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
|
||
|
|
; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
|
||
|
|
; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
|
||
|
|
; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
|
||
|
|
; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
|
||
|
|
; RV32IZFINXZDINX-NEXT: ret
|
||
|
|
;
|
||
|
|
; RV64IZFINXZDINX-LABEL: fminimum_nnan_op_f64:
|
||
|
|
; RV64IZFINXZDINX: # %bb.0:
|
||
|
|
; RV64IZFINXZDINX-NEXT: feq.d a2, a1, a1
|
||
|
|
; RV64IZFINXZDINX-NEXT: bnez a2, .LBB4_2
|
||
|
|
; RV64IZFINXZDINX-NEXT: # %bb.1:
|
||
|
|
; RV64IZFINXZDINX-NEXT: fmin.d a0, a1, a1
|
||
|
|
; RV64IZFINXZDINX-NEXT: ret
|
||
|
|
; RV64IZFINXZDINX-NEXT: .LBB4_2:
|
||
|
|
; RV64IZFINXZDINX-NEXT: fadd.d a0, a0, a0
|
||
|
|
; RV64IZFINXZDINX-NEXT: fmin.d a0, a0, a1
|
||
|
|
; RV64IZFINXZDINX-NEXT: ret
|
||
|
|
%c = fadd nnan double %a, %a
|
||
|
|
%1 = call double @llvm.minimum.f64(double %c, double %b)
|
||
|
|
ret double %1
|
||
|
|
}
|
||
|
|
|
||
|
|
define double @fmaximum_nnan_op_f64(double %a, double %b) nounwind {
|
||
|
|
; CHECKIFD-LABEL: fmaximum_nnan_op_f64:
|
||
|
|
; CHECKIFD: # %bb.0:
|
||
|
|
; CHECKIFD-NEXT: fadd.d fa5, fa0, fa1
|
||
|
|
; CHECKIFD-NEXT: fsub.d fa4, fa0, fa1
|
||
|
|
; CHECKIFD-NEXT: fmax.d fa0, fa5, fa4
|
||
|
|
; CHECKIFD-NEXT: ret
|
||
|
|
;
|
||
|
|
; RV32IZFINXZDINX-LABEL: fmaximum_nnan_op_f64:
|
||
|
|
; RV32IZFINXZDINX: # %bb.0:
|
||
|
|
; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
|
||
|
|
; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
|
||
|
|
; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
|
||
|
|
; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
|
||
|
|
; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
|
||
|
|
; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
|
||
|
|
; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
|
||
|
|
; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
|
||
|
|
; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
|
||
|
|
; RV32IZFINXZDINX-NEXT: fadd.d a4, a0, a2
|
||
|
|
; RV32IZFINXZDINX-NEXT: fsub.d a0, a0, a2
|
||
|
|
; RV32IZFINXZDINX-NEXT: fmax.d a0, a4, a0
|
||
|
|
; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
|
||
|
|
; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
|
||
|
|
; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
|
||
|
|
; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
|
||
|
|
; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
|
||
|
|
; RV32IZFINXZDINX-NEXT: ret
|
||
|
|
;
|
||
|
|
; RV64IZFINXZDINX-LABEL: fmaximum_nnan_op_f64:
|
||
|
|
; RV64IZFINXZDINX: # %bb.0:
|
||
|
|
; RV64IZFINXZDINX-NEXT: fadd.d a2, a0, a1
|
||
|
|
; RV64IZFINXZDINX-NEXT: fsub.d a0, a0, a1
|
||
|
|
; RV64IZFINXZDINX-NEXT: fmax.d a0, a2, a0
|
||
|
|
; RV64IZFINXZDINX-NEXT: ret
|
||
|
|
%c = fadd nnan double %a, %b
|
||
|
|
%d = fsub nnan double %a, %b
|
||
|
|
%1 = call double @llvm.maximum.f64(double %c, double %d)
|
||
|
|
ret double %1
|
||
|
|
}
|
||
|
|
|
||
|
|
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
|
||
|
|
; RV32IFD: {{.*}}
|
||
|
|
; RV64IFD: {{.*}}
|